Electronic Design

SoC/ASIC Verification System Is Fast And Scalable

Targeting SoC/ASIC developers of projects from 3 Mgates to 180 Mgates, the latest generation of GiDEL’s PROC_SoC Verification System doubles the capacity offered by previous versions by incorporating Altera’s Stratix III EP3SL40 FPGAs.

The PROC_SoC has a flexible interconnect topology that allows any FPGA device to directly connect with large numbers of pins to any other programmable device in the entire system. Users match system interconnect to the topology of the design being verified. There are over 950 pins per FPGA available to connect to FPGAs on the same reconfigurable board, FPGAs on other boards in the same PROC_SoC module, FPGAs on any other PROC_SoC module in multiple-module PROC_SoC systems, or user’s I/Os.

The system is architected and designed to operate at system clock speeds up to 300 MHz. Test suites and real-time operation with embedded and application software will experience the shortest possible verification time and the most effective system integration before silicon for users.

Two scalable, multiple-board, card cage-based configurations are available. The PROC_SoC 10-3S module holds up to ten PROC6M, dual-FPGA, 6-million-gate boards. The smaller PROC_SoC 3-3S holds up to three PROC6M boards. Capacities are 60 million and 18 million ASIC gates respectively. Each PROC6M board has two, interconnected, high-speed Altera Stratix EP3SL340 FPGAs and 256 Mbytes of onboard DRAM, or 2.56 Gbytes for each full PROC_SoC 10-3S module, and 768 Mbytes for the PROC_SoC 3-3S. Each PROC6M has over 1400 FPGA I/Os, which are brought to 118-pin edge connectors for user-allocated FPGA-to-FPGA interconnection.

The PROC_SoC system includes a comprehensive suite of software tools for implementing and debugging designs. The PROCWizard Software manages the data and integrates the files generated by tools for partitioning, design mapping, synthesis, place and route, and debug trigger logic and data capture. For each user's development environment, PROCWizard will generate a dedicated driver with optimized performance. This enables fast setup and running of comprehensive test benches from a host across a network to the verification system, and co-development with software development tools running on a host.

With the PROC_SoC System, tests will run the fastest of all comparable systems, and hard-to-reach bugs are found quicker, it’s claimed. There are various methods of capturing data and debugging designs to meet the needs of teams at different phases of their projects. Debugging can use both distributed memories within the FPGAs and on-board memories to capture signal data. The PROCWizard debug GUI enables direct access to the design I/Os and running of tests. Scripts are automatically generated of test processes for replay. The configurable multi-port, on-board memories can be easily set up to capture data from thousands of probe points during testing with virtually unlimited depth. Also, with the supplied SignalTap software, or with debug IP specialist DAFCA’s ClearBlue software, probes can be set for broad visibility using internal FPGA memories.

Teams only purchase the capacity they require, and add more capacity as needed. The PROC6M boards fit into a PROC_SoC module card cages within compact cabinets. Multiple PROC_SoC modules can be used for extremely large designs. Further, multiple users can independently access different reconfigurable boards in the same PROC_SoC module for independent designs and block-level regression tests. Fast/Gigabit networking interfaces to the PROC_SoC modules dynamically allow the system to be directly linked to various computers for running the test benches and for fast device programming.

PROC_SoC System delivery times are 4-6 weeks ARO. Prices start at about $30,000.

GiDEL Ltd.
www.gidel.com

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