It’s never been more important than in the current economic climate to get products to market with development costs held as low as possible. One of the ways that systems manufacturers can achieve that goal is through power analysis. After all, it wasn’t that long ago when all ICs ran on 5 V. But since then, we’ve seen voltage requirements spiral down to as low as 0.9 V. Complicating these matters even further, many ICs have multiple voltage requirements within the same package.
What does all of that mean in terms of printed circuit-board (PCB) design? Basically, the job is a lot more complicated. When all of the ICs were living on 5 V, a designer could devote an entire ground plane and power plane to that single voltage. Today, the plethora of voltages coursing across a given PCB means separate power-distribution networks for each of them. It’s simply not practical to devote a power/ground plane to each voltage. You end up with planes that are segmented and fragmented, with designers trying to jigsaw in as many as 30 different power networks on as few board layers as possible.
A related complicating factor is decoupling capacitors, or decaps. With so many power planes carrying low voltages, damping of noise is a critical issue in eliminating switching problems. Decaps are typically sprinkled around the board to hold down noise, but doing so indiscriminately drives up costs in terms of board area, manufacturing, and, of course, the capacitors themselves.
The goal, then, is to design and optimize PCBs with as few layers as possible while still supporting the myriad voltage requirements of modern ICs. Designers want to do all of this while using as few decaps as are needed, placing them in the proper spots and in the correct values to control noise and ground bounce.
In the past, designers would approach power-network design by reading the IC vendors’ guidelines and taking a conservative approach. Measures might include using more area than necessary on split power planes and more decaps than required. They would prototype the board, analyze it in the lab, debug problems, and then start over. It’s an inexact approach that takes too long and is often too expensive.
AN ALTERNATIVE APPROACH
A better approach is to consider power integrity and, indeed, signal integrity much earlier in the PCB design process. Even during the schematic- capture phase, designers can be doing what-if scenarios for both power and signal integrity. One tool that permits this kind of work, as well as full electrical analysis of PCB designs, is HyperLynx PI , a power-integrity analysis package that covers a wide range of ac and dc analyses.
On the dc side, a common issue on PCBs is insufficient voltage reaching a given IC, leading to malfunction. Closely related is the problem of high current densities in voltage island “neckdowns” and vias, which can cause dielectric or via breakdowns. HyperLynx PI can find these areas in which there are excessive voltage drops and high current densities, telling designers where they would need to add metal to traces and/or transition vias between layers. These analyses can be done either before or after the circuit board is laid out.
Simultaneous switching is the bane of PCB designers from a power-integrity standpoint. Consider what happens when an IC’s 32 outputs all switch at the same time, drawing a current spike. The power plane that’s feeding that IC becomes, in effect, a transmission line and serves as a medium for reflected and standing waves that propagate noise throughout the system.
The “fix” for simultaneous- switching noise is decaps. The problem, though, is where to put them, how many should be used, and what values they should be. Through its ac power-plane analysis, HyperLynx PI identifies characteristic power-delivery network impedances across all frequencies. It determines decap values, numbers, and mounting locations. This operation can be performed either before or after the board is routed (see the figure). Users can experiment with power plane spacings and decap locations as well. It also provides a view of noise propagation from power pins and vias.
Through use of HyperLynx PI’s various forms of analyses, PCB designers can have a much better shot at designing a power-distribution network that uses the least number of layers. Those layers will deliver the proper voltages and be properly decoupled so that board size and cost are within budget. Finally, by squelching current-density issues, the board will have greater long-term reliability.
HyperLynx PI is available now with prices starting at $35,000. It integrates with Mentor’s Expedition Enterprise, PADS, and Board Station PCB design flows as well as with third-party board design environments such as Cadence’s Allegro and Zuken’s CR 5000. Mentor Graphics