Compliant with SONET/SDH and Gigabit Ethernet standards, the Si5020 multi-rate clock and data recovery (CDR) chip requires only 16 sq. mm of board space, reportedly making it 5X smaller than comparable CDRs. It is also said to dissipate 50% less power. The IC employs a proprietary architecture called DSPLL to simplify achieving SONET/SDH jitter compliance in multi-gigabit fiber-optic communications systems, such as optical transceivers, routers and test equipment. The DSPLL architecture uses digital signal processing techniques to eliminate the need for external loop filter components. By placing all PLL circuitry on-chip, sensitive noise entry points are eliminated. The Si5020 is the first member of the new SiPHY family of high-speed physical layer ICs and is designed for high-speed serial communication systems, where it serves to recover timing information and data from a serial input at OC-3, OC-12, Gigabit Ethernet, OC-48 with forward error correction, and the equivalent SDH rates. The device is housed in a 20-pin micro-lead package (MLP), consumes only 300 mW using a 2.5V supply, and has a starting price of $73 each/1,000. The Si5018, a version of the device for fixed-rate applications, is also available for $59 each.
Company: SILICON LABORATORIES INC.
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