Electronic Design

Sonet/SDH Transceivers Add 8-Bit Interface And Deliver Best In Class Jitter Performance

Sonet/SDH systems continue to dominate long-haul and metro networks because of their high speed and flexibility. Chip companies are helping to keep it that way with a continuous stream of improved ICs to give Sonet/ SDH a performance kick and a price reduction now and then.

For example, Exar's OC-1/OC-2/OC-3 transceiver chips address cost-reduction trends and increased design margin needs on new and legacy line card designs in add-drop multiplexers, cross-connect equipment, and multiservice switches and routers. The XRT91L31 and XRT91L32 both are footprint-compatible with competing SONET/SDH transceivers (see the figure).

This compatibility lets system designers adopt these chips in existing designs without major board modifications while taking advantage of significant performance improvements. Designers now have a range of transceiver choices for OC-3, OC-12, and OC-48 equipment. The Exar transceivers don't show any cross talk between the transmit and receive sections under asynchronous modes of operation, enabling superior signal integrity.

The XRT91L31 and XRT91L32 operate at the standard 155.52- and 622.08-MHz Sonet/SDH data rates. The chips contain parallel-to-serial and serial-to-parallel converters, a clock multiplier unit (CMU), clock and data recovery (CDR) functions, and a Sonet/SDH frame and byte boundary detection circuit.

The main interface is an 8-bit low-voltage transistor-transistor logic (LVTTL) parallel bus running at 77.76 Mbits/s in STS-12/STM-4 mode or 19.44 Mbits/s in STS-3/STM-1 mode. A 19.44-MHz crystal is used to generate the clock. The on-chip CDR can be disabled so an external clock can be used.

Both chips support loop-back modes that provide complete system testability. The loop-timing mode lets users run the transmitter and receiver synchronously. The chips incorporate circuits that detect and generate various alarms and status outputs to provide immediate system alerts and fault coverage.

Also, the chips meet the G.958 Sonet jitter transfer specification. Exar's phase-locked loop (PLL) technology provides a simpler solution compared to some traditional discrete component implementations that have been used in competitive devices. The devices produce less than 5 mUI (milliunit interval) rms of jitter in normal and loop-timing modes. Jitter tolerance is better than 0.6 UI, giving designers more jitter margin in their designs.

Finally, the XRT91L31 and XRT91L32 consume very little power, eliminating the need for a heatsink or a more elaborate arrangement for temperature management. With a 3.3-V supply, the dissipation is 660 mW in STS-3/STM-1 mode or 800 mW in STS-12/STM-4 mode. The XRT91L31 comes in a 10- by 10- by 2mm 64-pin package, while the XRT91L32 uses a 10- by 10- by 2-mm 100-pin package.

In lots of 1000, the XRT91L32 costs $24, and the XRT91L31 costs $26.50.

Exar Corp.
www.exar.com

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