Electronic Design

Speedy Dual-Port Memories Deliver Data At Up To 36 Gbits/s

According to their developer, Cypress Semiconductor, the latest FullFlex dual-port memories offer 150% more throughput than their competitors. With a maximum 36-Gbit/s throughput, the company says these chips also are the first dual ports to use 90-nm process technology.

As a result, the FullFlex chips deliver performance compatible with wireless systems, image processing, instrumentation, and storage-area network and widearea network applications. FullFlex devices will range in density from 0.5 to 36 Mbits/chip with bus widths of 18, 36, or 72 bits (see the figure).

These dual-port devices can serve as interprocessor communications memory as well as single-processor companion memory. When used as a companion memory, they deliver the full 36 Gbits/s of dedicated bandwidth independent of the system read/write ratio. When used for interprocessor communications, a rich set of built-in features simplifies board-level design and allows high-bandwidth data transfers between processing elements.

Able to operate at system clock speeds of 250 MHz, the FullFlex memories employ 72-bit data buses. They also offer easy interoperability. According to Cypress, these chips are the only dual-port devices to offer double-datarate interfaces, doubling the data throughput while maintaining existing pin counts. Additionally, their variable impedance matching, deterministic access control, user-selectable I/O standards, and echo clocks ease system integration.

The variable impedance matching eliminates the need for multiple impedance matching resistors by automatically performing impedance adjustments on I/O drivers to counterbalance environmental changes. This also simplifies the board design. The deterministic access control reduces processing delays and simplifies system troubleshooting by providing controlled, deterministic feedback in cases of data collisions.

The I/O buffers can be set to handle any of the multiple interface levels on a port by port basis—3.3-V low-voltage transistor-transistor logic, 2.5/ 1.8-V low-voltage CMOS, or 1.4- to 1.9-V extended high-speed transceiver logic (eHSTL). The echo clock provides a companion reference clock to outbound data, preventing data-capture-delays caused by onboard parasitics and permitting more efficient system operation.

FullFlex devices with 72-bit bus widths will come in 484-contact plastic ball-grid array packages, while the 18- and 36-bit memories will come in 256-contact packages. Pricing for the 4-Mbit FullFlex dual-port memory starts at less then $50 each in lots of 10,000. Samples are immediately available.

Cypress Semiconductor Corp.
www.cypress.com

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