Electronic Design

Streamlining The ASIC Design Process

Rising ASIC complexity has thrown an expanding minefield of obstacles in the way of achieving first-pass silicon in a predictable time period. Traditional design processes are fragmented, and cross-domain verification is often ineffective. Furthermore, the long simulation runtimes now common with modeling, extraction, and re-simulation of parasitics can kill schedules or delay development. Most importantly, these design issues vary widely from one application arena to the next.

Designers building products for the personal entertainment market, for instance, must grapple with the unique challenges inherent in system-on-a-chip integration and validation. Intellectual-property (IP) integration and functional verification often stand in the way toward rapid and predictable development.

In the wired networking arena, on the other hand, extremely high-speed I/Os present a different set of problems. Package and board design, plus the potential signal-integrity issues associated with high-speed chip I/Os, pose a unique set of challenges on their own.

Still other challenges await product developers in the wireless market. They must deal with stringent power budgets that often conflict directly with their attempts to integrate noise-sensitive RF blocks into the design. Compact product footprints require a high degree of integration that can quickly complicate mixed-signal simulation and hardware/software verification.

The EDA industry has begun streamlining the ASIC design process is by taking a new, highly vertical market approach to problem-solving. For example, Cadence designed its new kit strategy to circumvent many of these issues. The kit contains interoperable, cross-domain tools that target the key design challenges in a specific vertical market. As a result, designers can more efficiently create application-specific designs. Each vertical market segment then has its own kit to better address the specific requirements of that market segment.

Rather than drop a new set of tools into the designers' laps and let them figure out how to apply it to their design flow, the kit approach helps users apply EDA technology to the specific needs of their market segment. It starts with a verified design methodology, platform flows, and a comprehensive suite of tools, IP libraries, and simulation examples targeted at the exact challenges that designers face in their application segment. That methodology is then demonstrated on a market-representative reference design, which often presents many of the same design issues faced by the user.

But this approach doesn't stop there. Those methodologies are then mapped to the user's specific needs, whether they be the low-power design challenges found in a wireless product or the IP integration issues inherent in a personal entertainment design. Then Cadence delivers the training and consulting services needed to apply the demonstrated methodology to the specific project. Implicit in this new approach is a tight partnership between Cadence and its customer.

Designers using this new approach get shorter, more predictable design cycles and improved productivity. Perhaps just as importantly, though, it enables them to spend more of their precious resources and time on differentiating their design and beating the competition instead of optimizing their design infrastructure.

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