The industry has seen a rather rapid ramp-up in the deployment of PCIe native endpoint solutions. As a result, many legacy PCI systems are unable to host the latest feature sets in networking, graphics, storage, video capture, and other add-in cards that make PCs useful in a range of applications.
Typically, the most advanced features and performance levels are found in the newest PCIenative chips. These chips are deployed on add-in cards that interface with PCIe-based PCs. However, the demand remains great for new cards for use in PCI-based computer systems.
One solution now available— reverse-mode PCI-to-PCIe bridges—can extend the lives of legacy PCI systems. These bridges go in front of the PCIe-native chip on the add-in card to form a PCI version of the same card.
This article examines reversemode bridging and how it differs from forward-mode bridging. In addition, it looks at a PCI graphics- card application example that uses PCIe-native silicon along with a reverse-mode bridge for use in a legacy PCI-based PC.
WHAT IS REVERSE BRIDGING?
When the PCIe-to-PCI bridge was first envisioned, it was aimed at forward-mode applications— that is, for bridging a PCIe root complex to one or more PCI (or PCI-X) buses. This function was included in the first PCIe chipsets to provide PCI (or PCI-X) connectivity on early PCIe system boards. The most common example is the use of a forward-mode bridge to create PCI slots on a PC motherboard. Another common example is using a PCIe-to-PCI bridge (again, in forward mode) to deploy PCI-based endpoints on PCIe system boards.
The functionality of a forwardmode bridge is defined in the PCI Express to PCI/PCI-X Bridge Specification Revision 1.0. Appendix A defines the Conventional PCI/PCI-X to PCIe Bridge functionality. Here, reverse-mode bridging is described in detail.
Figure 1 compares a forwardmode versus a reverse-mode application. Most first-generation PCIe-to-PCI bridges don’t include reverse mode. More recently, however, several devices have emerged with reverse mode.
As shown in Fig. 1, a forwardmode application has the PCIe link as the upstream port of the bridge. In a reverse-mode bridging application, the primary bus of the bridge is the upstream port, being the closer of the bridge’s two ports to the host CPU.
PCIe-to-PCI bridging devices that include both forward- and reverse-mode operation, such as the PLX PEX 8111 bridge, are now commercially available. A device is placed in reverse-mode via a strap option (when the FORWARD ball is pulled low).
In reverse-mode, the bridge presents a Type 1 configuration space header on the PCI bus. In this mode, the PCIe interface has no PCI-compatible configuration registers. This means the PCInative host CPU can configure devices that are downstream from the bridge, while no configuration cycles can originate on the PCIe side of the bridge. This is the opposite of forward mode. Three sets of Type 1 configuration space header registers define the bridging operation between the PCI bus and the PCIe interface.
In reverse mode, the bridge makes it possible for a PCI host to access the downstream PCIe configuration registers, using PCI memory transactions. A bridge in reverse mode also detects completion with control register status from a downstream PCIe device. A device-specific control register determines the bridge’s response in reverse-mode when a PCI-to- PCIe configuration transaction is terminated with a configuration request retry status.
One interesting feature of the PCIe Bridge Reverse-Mode specification involves error handling. It requires that a PCI-to-PCIe bridge generate a system error (SERR) message in response to either fatal or non-fatal PCIe error messages. Since an SERR on the PCI side will cause a system hang— an unwelcome result of a nonfatal error on the PCIe side— bridges like the PEX 8111 implement a masking bit, which allows the user to determine whether the SERR will be generated.
The data paths and control logic for reverse-bridge mode are the same as those used for forward mode, except that address decoding based on the configuration registers resides on the PCI bus. Adding reverse mode to a bridge design adds significant complexity and silicon area; hence, most bridges don’t support this feature.
PCI ADD-IN CARDS USE PCI EXPRESS NATIVE SILICON
Reverse-mode bridges come into play when creating a PCI add-in card using PCIe native silicon. This is a handy option for designers, since many of the latest features and performance levels are found in PCIe-native chips. Figure 2 shows a typical deployment of a reverse-mode bridge in front of a PCIe native endpoint, in which the endpoint is a graphics processor (GPU). Several applications are appearing with this topology.
Graphics cards with PCIe-native silicon have bounced around the market for several years, while few if any PCI-native graphics chips have been designed since PCIe’s emergence. However, a large market still exists for PCI graphics cards, due to the massive installed base of PCI gaming systems that need to upgrade their video capability, and because limited PCIe slot availability in current systems often forces system integrators to use a PCI slot for graphics.
As a result, recent graphics cards designs use a PCI-to-PCIe bridge in front of a PCIe native graphics chip. This gives PCIbased systems access to the latest GPU features, such as DDR2 memory support, 400+MHz engine clocks, and dual-link DVI.
Figure 3 shows a low-cost, boxto- box connection operating for a few meters over low-cost CAT7 cable. It allows cost-efficient legacy PCI systems to communicate over a x1, x2, or x4 PCIe link. The end result is very high data transfer rates at low cost.
The PEX 8114, a PCIe-to- PCI/PCI-X bridge, can be configured in a x1, x2, or x4 link width, providing up to several hundred megabyte-per-second transfers. In this topology, the host system uses a reverse-mode PCIeto- PCI bridge, while the slave system employs a forward-mode bridge. Both bridges reside on PCI add-in cards that sit on each system’s 32-bit PCI bus.
In the host system, the bridge’s upstream port is the PCI side of the bridge, requiring the reversemode configuration. The downstream port of the bridge is a x1 PCIe link. This link directly drives the cable for a few meters without the need for a repeater.
The slave system’s forwardmode bridge is configured with the x1 PCIe link as its upstream port and the slave’s 32-bit PCI bus is its downstream port. This topology is useful for applications like remote data storage, remote data acquisition, and systems that require physical isolation between the user interface, the CPU, and/or the hard drives. Also, PCIe’s hot-plug feature lets you design interchangeable I/O and storage modules or boxes, with on-the-fly replacement.
Most current PC, server, and workstation chipsets are PCIenative, with at least one or two PCIe slots. But legacy PCI chipsets have no PCIe connections. A reverse-mode bridge is thus required to add a PCIe slot and/or a PCIe endpoint chip to motherboards using these chips.
In summary, reverse-mode bridging can breathe new life into legacy PCI systems, allowing PCIe-native silicon endpoints to be deployed on PCI add-in cards. Applications from graphics cards to box-to-box interconnection cabling and new system boards use reverse mode to broaden their connectivity range, and thus boost potential market share.