Chip-scale packages were introduced to the semiconductor industry in the early 1990s to address the need for reduced size and weight in consumer products, like camcorders, cameras, and cell phones. Japanese OEMs, such as Sony and Sharp, first realized the benefit of this package type and then implemented chip-scale packaging (CSP) across many product platforms. In the mid- to late '90s, the cell phone emerged as the killer application for chip-scale packaging.
Since they were first introduced, many types of CSPs have been developed. Some utilize microleadframes. Others use polyimide, BT, or FR-4 package substrates. Each option has its pros and cons, but all save board space and meet the chip-scale requirement that the packaged device be less than 1.2 times the die size. Yet in recent years, OEMs have pushed the semiconductor industry to develop even smaller packages.
THE CHALLENGES OF WLP
One next-generation CSP option is wafer-level packaging (WLP), where the package is exactly the same size as the die. While WLP offers very high silicon density per unit of printed-wiring-board area, there are many obstacles to its broad adoption. The biggest of these is the lack of a manufacturing infrastructure for assembly and test at the wafer level. For very small, low-I/O devices, WLP can provide a cost-effective solution as the package implementation costs can be spread over a great many components.
But for larger, higher I/O devices, other concerns regarding WLP emerge, like the inability to establish the interconnection standards required for multisourcing of components. Standardization of wafer-level packages is difficult because integrated device manufacturers use different design methodologies to optimize for functionality, performance, cost, and manufacturability. As a result, wafer-level packages vary from vendor to vendor with respect to the size of the semiconductor device and the location of its electrical contacts.
Although differences in contact location could be eliminated with a redistribution layer, device size can't. That's partly because integrated device manufacturers make their devices as small as possible to maximize the number of die per wafer, which lowers manufacturing cost. Also, when interconnect standards are in place, the interconnect array is frequently larger than the die. This is problematic for a technology that requires the package to be the same size as the die. Die size could be increased, but cost would rise significantly.
These and other issues have driven the industry to continue to evaluate alternatives for reduced product size and increased silicon density. A solution enjoying wide adoption today is the stacked multichip package (MCP), sometimes called 3D packaging. MCPs offer many benefits over WLP. The foremost advantage is that the MCP uses the existing infrastructure, including the same equipment, materials, and processes as chip-scale packages. Stacking multiple dies within one package is an extension of the chip-scale packaging process.
MCPs tend to drop right into the installed manufacturing base with minimal modifications of equipment or materials. Some consideration is made for the location of the electrical contacts on each device stacked. Otherwise, the assembly operation is very similar. The ability to leverage existing infrastructure has encouraged adoption, while ensuring low cost and broad availability. The MCP approach also produces higher silicon density—perhaps up to a fivefold increase—than WLP. Other factors like compound yield can limit the number of chips that may be stacked. However, the industry continues to optimize MCP approaches to maximize its value, enabling next-generation electronic products to be developed today.