Christmas is coming early for system designers who want up to a terabyte of bandwidth as well as simplified pc-board layout. As part of its Terabyte Bandwidth Initiative (TBI), Rambus responded with a neat idea—place more data bits on a given pin for a given clock transition than the typical one-bitper- pin per transition. The company also has devised a technology that allows for mismatches in trace length.
For example, the DDR3 protocol allows for one datum bit per data pin per clock transition. So at a clock rate of 500 MHz, the bandwidth would equal 1 Gbit/s. Yet the TBI would allow for a 16-fold data-rate increase by taking that same 500-MHz clock and, using a phase-locked loop, multiply the clock 16-fold and clock the data on both edges as before. As a result, using the same 500-MHz clock would provide a bandwidth of 16 Gbits/s.
So how do we get to a terabyte of bandwidth? Simple: 16 DRAM chips each providing 16 Gbits/s per data link on a 32-bit-wide bus − 16 ×16 Gbits/s × 32 bits − 8 Tbits/s or 1 Tbyte/s. Now all we need is a system-on-a-chip (SoC) with enough address, data, and control lines to handle all the data. This is where the second phase of this Christmas present comes in—simplified layout.
Three factors will ease layout while improving signal quality using this technology. First, there are fewer data, address, and control pins. Second, the memory architecture is fully differential, including command, address, and data. Third, a technology called FlexPhase allows for fine-grained per-pin timing adjustment, which compensates for trace-length differences by transmitting data at different times on each trace. Therefore, by the time the data gets to the receiver, both signals are aligned.
“Our FlexPhase technology has proven useful in today’s XDR memory systems for achieving high signaling rates, compensating for manufacturing variations, and eliminating the need for trace-length matching,” says Steven Woo, technical director for Rambus. “We’ve carried this technology forward into the Terabyte Bandwidth Initiative as these issues become more challenging as data rates increase.”
It doesn’t matter if we’re talking about two traces carrying different phases of a given differential pair or different signal members of the same bus. The length can vary significantly (inches) for either. Meanwhile, the initiative includes a new two-wire address and command interface.
“With the Rambus FlexLink C/A Command/ Address interface technology, we have converted the C/A signals from a wide, slow multidrop bus to a narrow, high-speed point-to-point link,” says Woo. “This reduces the number of pins and area dedicated to the C/A interface, reducing overall cost.”
As a proof of concept, the company
demonstrated a test board with two
DRAM chips connected to an SoC concept
device at the Rambus Developer
Forum in Tokyo last month (Fig. 1). The
demonstration also clearly showed the
signal-integrity improvement of the signals