Good design practice mandates liberal use of decoupling capacitors (decaps) in the design of both IC packages and pc boards. But where should they be placed for optimal power delivery? Many designers resort to guesswork or, worse, overdesign when it comes to decaps. It's easy to forget that those decaps take up space and add cost whether they're actually helping smooth out the power picture or not.
Sigrity's OptimizePI comes into the decap fray to provide minimum-cost decap selection and placement to achieve the desired performance for the package or board's power-delivery system. With the tool, designers can assess their power-delivery system's performance against the design's specifications.
Through interactive "what-if" decap placement and selection trials, users can minimize decap cost for a specified level of power performance. They can then assess that performance in concert with the cost tradeoffs and make more informed decisions.
The tool considers both component and manufacturing costs during its automated selection of decaps. Using OptimizePI, users can reclaim IC-package or board area from unnecessarily placed decap pads and vias. This freed-up space can help them meet overall product-size constraints, perform more effective escape routing, and potentially reduce the number of layers in the board stackup for added cost savings.
OptimizePI will be available in June. Pricing starts at $35,000 for an annual license.