Standing as they do as the bridge between the digital and mixed-signal world of System-On-A-Chip (SOC) cores and the largely analog world of the circuit board, I/O cells are an increasingly difficult beast for designers to tame. Not only must I/Os typically comply with one of a rapidly expanding number of published electrical standards, but they must do so across a range of operating environments that may not have been considered by those who characterized the simulation models.
The fact that a published electrical specification exists for a given type of interface cell can make it seem as though using it is relatively simple. Yet that specification can never hope to anticipate all of the vagaries of that cell's real-world environment. Thus, SoC or ASIC designers attempting to coax their I/Os to simulate properly often find that the models work as expected within a given range of conditions but not outside it. If they expect their end product to see conditions at these design corners, what ensues is a long process of ascertaining what measurements must be taken, determining how to take them, and writing applicable Spice decks, a task that few designers are eager to take on.
With I/Os so critical to overall timing and power closure for ASICs, designers need more than ever to be able to accurately anticipate their real-world behavior. To that end, SiliconSmart IO from Silicon Metrics addresses the growing concerns of ASIC and SoC design teams regarding I/Os and their conformance with industry-standard specifications (Fig. 1). Not only does it automate the process of validating specification compliance, it does so with Spice-accurate characterization. If need be, the tool will automatically recharacterize the models to accurately reflect the I/Os' performance in the context of the overall design.
Consider that when I/Os are designed, they're usually intended for exclusive use in some limited set of electrical and environmental conditions. For example, a vendor might design the I/O to work with a pc board from a specific provider that might be willing to accommodate inadequacies or noncompliant aspects of the I/O cell by compensating in the board's design. If that vendor should later choose to sell that same I/O for use in new applications, those regions of noncompliance on the I/O's process voltage-temperature curve could necessitate a major redesign.
There's also the issue of the quality of characterization applied to cells by library vendors. To some consumers of off-the-shelf I/O intellectual property, characterization is lacking. "Do we really get good models from the library vendors?" asks Terry Hulett, vice president of engineering at Banderacom, a fabless semiconductor company in Austin, Texas. "I've convinced myself that no, we don't. Do I trust vendors to deliver me I/O libraries that are going to meet spec? To tell you the truth, no, I don't."
According to Rob Aitken, manager of ASIC design methodology at Agilent, the need for a tool like SiliconSmart IO is a matter of consistency, especially for those in the fabless IC world. "We get I/O intellectual property of all sorts from a bunch of different sources," Aitken says. "In order to produce working chips, it's necessary to have a consistent characterization methodology."
Preparing I/O models is typically a three-stage process. First, the models must be validated for compliance with standards across all expected operating environments. Next, they're characterized, meaning that the designers must determine an I/O's response to various environmental and electrical conditions. Lastly, models must be published in an error-free, accurate form.
The validation issue is a particularly critical one considering the plethora of I/O standards, driven by advances in process technology that force circuit redesigns to match the shifting interface specifications. Validation and characterization have typically been carried out using manual processes or internally developed scripts, an option made dicey by the explosion of I/O standards.
On the validation side, SiliconSmart IO allows both I/O-cell developers and IC designers to analyze cells for compliance against published electrical specifications. Currently, the tool supports USB low-speed and full-speed (USB 1.0 and USB 1.1) and low-voltage differential signalling (LVDS).
Guruprasad Rao, director of engineering at Silicon Metrics, says that SSTL-2/3 and USB 2.0 (high-speed) will be added in the next quarter, followed by I2C, I2S, PCI, PCI-X, AGP, and HSTL.
"We interpret industry-standard specifications and extract the relevant electrical limits implied or explicitly stated by the specification," Rao says. These limits are then exercised against acquired measurements across the expected operating range of the cell. The measurements, test circuits, limits, and stimulus for all the tests in a specification compliance suite are packaged into a Specification Compiler for a particular standard.
By delivering the compliance knowledge base associated with each standard within SiliconSmart IO, the tool relieves designers of the need to repetitively interpret these complex standards as they're applied to each iteration of an interface cell. The tool's consistent application of the standard to I/Os gives the characterization process the consistency Aitken is seeking. Instances of a cell's noncompliance are reported in the context of measurements de-scribed in the external specification.
SiliconSmart IO offers an automated and unbiased process for validating an I/O design's compliance. Specifications are provided in ASCII format, enabling users to enhance them to meet their company's internal requirements. Such a requirement, for example, might facilitate support for a military or aerospace application. Users can also adjust margin tolerances to account for simulation style and process variances. A final compliance report identifies any specification that was overridden to help document changes to the specification.
Within the compliance report is a summary of specification rules and a rollup indicating compliance success or failure. Details for each measurement are provided through dynamic links. The report's data is presented in XML for easy reading with any Web browser or for easy modification (Fig. 2).
Hulett says the primary value of a tool like SiliconSmart IO is its encapsulation of the body of knowledge about I/O standards. "As long as the chip works, my customers don't see an internal discrepancy in characterization," he notes. "But with I/O, if it's supposed to meet an SSTL-2 spec or a PCI-X DDR spec, they'll see that. Even if it looks like it's meeting timing, it won't have the right rise and fall times. So it's valuable to have a tool that not only characterizes I/O, but checks it against a spec."
Not only must I/Os be compared to a specification, they must also be characterized, a process that involves a maze of interrelated parameters that vary from one cell type to another. I/Os are intrinsically analog in nature, a fact borne out by characteristics like nonmonotonic waveform distortions, overshoot and undershoot, ringing, and clipping. Traditional approaches to characterization force engineers to make many judgment calls amid a slew of simulation runs. Mistakes can mean poor models.
Characterization is a central element of SiliconSmart IO. It performs characterization for timing and power in context of the overall design. The tool's measurement acquisition technology accounts for the analog and mixed-signal complexities surrounding I/O pads. Various analog characteristics and measurements are made automatically.
The tool currently packages measurements like hysteresis, VIL, VIH, VOL, VOH, crossover point detection, common-mode rejection ratio, and input impedance in specification compliance packages like USB low-speed/full-speed and LVDS. These measurements are performed while taking into account such real-world issues as bond-wire inductance, off-chip transmission line loads, and non-idealized supplies.
There's support for phase tolerance measurements for clocks, and the software differential pairs and handles complex power measurements accounting for pin currents and all defined voltage sources. It can describe arbitrarily complex load structures, including RLC modeling for solder junctions, bond wires, and leadframes. It also handles driver conditions, including ideal, emulated, and full active drivers and their connection networks.
Hulett says it's this ability to characterize I/Os in context that makes the tool shine. "If, for example, you had four I/Os all sharing one power-ground pad, you could evaluate how the inductance of the power supply impacts the characteristics of the I/O," he explains.
During characterization, the design team essentially creates an arbitrary network that reflects the I/O pad's context. The tool derives this network from an I/O functional description, an extracted netlist, and process models.
Meanwhile, the tool's I/O Methodology Compiler uses a behavioral description of the cell to extract all the measurements relevant to a digital model that can be used in a full chip timing or power analysis tool. This is done using a binary decision diagram-based arc extraction engine that uses the electrical specification of a cell to create packaged tests much like the packaged tests generated by a specification compiler.
The I/O Methodology Compiler lends itself to interfacing the tool to a variety of commercial and proprietary simulators, including SmartSpice, Star-HSpice, and Spectre (available in this quarter). SiliconSmart IO also features a graphical user interface and shell-based batch mode interface. Built for use in a .tcl environment, the tool can be driven by custom command structures to let users instantiate models in various tool flows.
Virtually any kind of I/O can be characterized and have models automatically generated. Some designers work with custom I/Os that do not necessarily conform to a published specification. Over the next two quarters, the tool will be incrementally upgraded to validate what Rao calls design compliance rather than specification compliance. The intention is to apply the same programmatic constructs the tool uses internally to build specification compliance packages for internal specifications.
Support is built in for complex I/O port specifications, including differential ports, voltage- and current-referenced ports, and analog ports. There's complete functional support for bi-directional cells, arbitrarily complex sequential functions, illegal paths and states, and digital, nondigital, and analog functions. The tool also can handle cells of arbitrary size and is limited only by the capacity of the target simulator. Multiple strength pads in the context of SSTL will be supported in the next major revision, expected in Q4 of 2002.
Once characterized, models must be published. Currently, the tool supports Synopsys .lib (Liberty) models for timing and power. According to Rao, Silicon Metrics will add Verilog and IBIS over the next quarter, to be followed by other model formats like ALF and TLF.
Price & Availability
Pricing for SiliconSmart IO is modular. However, an entry-level package starts at $90,000. The tool is available now with support for Solaris and HP-UX platforms, with Linux support coming later this year. Electrical specification compliance validation will be available for LVDS, SSTL, and I2C in the current quarter. USB 2.0, PCI, PCI-X, and AGP will be available in the fourth quarter.
Silicon Metrics Corp., 12710 Research Blvd., Suite 300, Austin, TX 78759; (512) 651-1500; www.siliconmetrics.com.