Electronic Design

Transceiver Chip Set Wrings Out GSM Phone Costs

A highly integrated CMOS three-chip set replaces many components and lets designers focus on baseband and data-transmission features.

Designing a low-cost multiband cell phone just got easier. Silicon Laboratories' Aero chip set provides a complete two- or three-band GSM transceiver using only a few external components. This three-chip set includes the Si4200 transceiver IC, the Si4201 baseband interface, and the Si4133T synthesizer IC. Silicon Labs' claim to fame is a 100% CMOS highly integrated chip set that significantly reduces the number of discrete components needed while lowering costs and greatly minimizing the number of manufacturing steps. Furthermore, the resulting circuits take up less board space and use less power.

As cell phones and the wireless infrastructure evolve from the current 2G digital systems toward the elusive 3G, both phones and basestations must support not only legacy analog systems, but also two or more digital standards and bands as well as newer 2.5G features. A typical phone might have to cover two or more of the following: the U.S. 800-MHz band, the U.S. 1900-MHz PCS band, the European 900-MHz band, and the 1800-MHz DCS band.

Newer phones and basestations are increasingly including more advanced data-transmission facilities. The most popular for TDMA systems, like GSM, is general packet radio service (GPRS). This system provides packet data transmission by stealing time slots from the eight voice channels. A data rate as high as 115 kbits/s is possible, but most units will only cover up to about 56 kbits/s.

With such data-transmission capability inside the cell phone, the emphasis in design shifts from RF to the baseband section, where the various data applications will be implemented. Luckily, designers can rely on chip sets like the Aero to take care of the RF part of the design while reducing the space on the pc board as well as the number of discrete components. Additionally, the Aero meets GPRS class 12 requirements.

The Aero chip set breaks new ground, as it greatly reduces the total number of components needed to implement the RF section (Fig. 1). Compared to today's typical handset, the reduction is dramatic, with 80% fewer components and 50% less board space required. The chip set eliminates the SAW IF filters, RF and transmit voltage-controlled-oscillator (VCO) modules, and dozens of discrete components.

According to Tyson Tuttle, Silicon Labs' RF products manager, "In one design, the RF section was reduced from 130 components in a 900-mm2 area to only 21 components in a 400 mm2 area. Over 100 components, mostly discrete, were eliminated. Just think of the savings in parts cost, procurement, inventory, board insertions, and manufacturing yield. On production runs of 10 million phones a year or more, over 1 billion parts are eliminated."

The design of the transceiver is pure CMOS versus the competition's bipolar or biCMOS approach. Using 0.18-µm processes, the die size is smaller and, therefore, less expensive. Also, the devices can be made in most digital fabs with higher yields.

The architecture includes a low-IF superheterodyne receiver with digital IF processing that interfaces to standard baseband chips (Fig. 2). The transmitter includes the upconverters, an on-chip transmit VCO with offset PLL, and drivers for the external power amplifiers (PAs).

The antenna is typically connected to a gallium-arsenide (GaAs) PIN transmit-receive switch. SAW filters provide the initial selectivity for the three GSM 900-MHz, DSC 1800-MHz, and PCS 1900-MHz bands. Discrete LC matching networks are used to connect to the differential low-noise amplifiers. Image-reject types of mixers downconvert the signal to an IF of 100 kHz.

Low IF Provides Advantages
This very low IF has several advantages. First, it greatly reduces the image rejection requirements, eliminating the need for image filtering after the LNA. Second, it permits on-chip IF filtering, thereby eliminating the requirement for an expensive and space-consuming external SAW IF filter.

The low-IF approach was chosen over the direct-conversion or zero-IF design because the latter is much more difficult to realize in a single chip. Direct-conversion receivers are extremely sensitive to dc offsets and greater 1/f noise. In addition, zero-IF designs suffer from local oscillator and RF self-mixing and second-order distortion of blocking signals.

Higher linearity in the low-noise amplifiers and mixers as well as better filtering can overcome these problems. But, this usually results in higher power consumption and a larger chip. While numerous direct-conversion receivers have been developed, notably Analog Devices' Othello chip set and proprietary designs by Nokia, Ericsson, Alcatel, and others, Silicon Labs chose the low-IF approach. It completely avoids these problems while providing all of the same benefits.

The 100-kHz IF signals are filtered by simple passive RC low-pass filters and fed to programmable gain amplifiers controlled by the received-signal strength indicator circuits. The signals are then digitized by two delta-sigma oversampling analog-to-digital converters (ADCs) running at 13 MHz.

The digital outputs are sent to the Si4201 IF-to-baseband converter chip, where they're downconverted to baseband by digital mixers. Digital IIR channel filters provide most of the selectivity for the radio. Finally, the outputs are converted to analog by digital-to-analog converters (DACs) to provide compatibility with existing baseband interfaces. Demodulation of the GMSK data is performed in the baseband circuits. In the future, it's expected that the digital outputs from the ADCs in the Si4200 will go directly to the baseband chip set. That will perform the mixing and filtering, eliminating the need for the Si4201 and further reducing space, cost, and power consumption.

On the transmit side, the GMSK I and Q signals from the baseband circuits are upconverted to an IF signal in the 400-MHz range. The synthesizer chip provides the necessary IF local oscillator frequency. The transmit signal is generated by an on-chip VCO that's part of an offset PLL whose inputs are the 400-MHz data signals and a signal from a mixer. This offset PLL design acts like a bandpass filter centered on the carrier frequency. The bandwidth is approximately 1.5 MHz, which helps attenuate any noise or spurious signals that might exist in the reference in the transmit output. It eliminates the need for off-chip transmit SAW filters as well.

Low-Power Drivers
Low-power driver amplifiers supply sufficient output to operate the two off-chip higher power amplifiers, one for 900 MHz and the other for both 1800 and 1900 MHz.

The Si4133T synthesizer provides all of the signals for the transceiver. The primary input signal is the clock from an external temperature-compensated crystal oscillator (TCXO) at 13 or 26 MHz (Fig. 3).

The chip contains three independent PLLs. Two RF VCOs are designed for center frequencies of 1900 and 1350 MHz, and the IF VCO is designed for a center frequency of 825 MHz. The output range is adjustable over a ±5% range. All components including the loop filters are fully integrated.

"One of the greatest challenges of designing this chip was the VCOs," Tuttle says. To eliminate the need for laser trimming, a unique closed-loop feedback circuit with a self-tuning algorithm is used to center the VCO frequencies

Immediately after power-up or a change in the PLL division factor, the synthesizer's self-tuning circuit goes into operation. Its goal is to set each VCO as close to the desired frequency as possible before the analog tuning varactors take over. This self-tuning feature causes a bank of capacitors to be switched in or out to zero in on the desired frequency. The VCO uses the inductance of the bond leads as part of its resonant circuit.

The IF VCO uses an external inductor, while the RF VCOs use only the bond-wire inductance and a short pc-board trace. The self-tuning circuit leaves the VCO frequency within 1% of the desired frequency. The transmitter PLL also uses the self-tuning feature.

The PLL frequencies are set by loading the appropriate binary word into the PLL dividers. This is done via a 22-bit serial data word from the baseband processor. The settling time meets the GSM specifications and is more than sufficient to meet the requirements for class 12 GPRS.

Price & Availability
The complete chip set includes the Si4200 transceiver in a 32-pin microleadframe package (MLP), the Si4201 baseband interface in a 20-pin MLP, and the Si4133T in a 28-pin MLP. Total cost for the chip set is $8.62 in quantities of 10,000. Samples are available now. Volume production will be available in the second quarter.

Silicon Laboratories Inc., 4635 Boston Lane, Austin, TX 78735; (512) 416-8500; fax (512) 416-9669; www.silabs.com.

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