EE Product News

Transceiver Does LVTTL-To-GTLP Translations

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Intended for medium-to-high performance (125 MHz) backplane applications, GTLP18T612 chip provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. The 3.3V, 18-bit LVTTL-to-GTLP Universal Bus Transceiver offers edge rate control to minimize noise on the GTLP port and provides 50 mA GTLP drive and 24 mA LVTTL drive. Other features are power up/down high impedance for live insertion, an external VREF pin for receiver threshold, and BiCMOS technology for low power dissipation. Bus-hold data inputs on the A port eliminate the need for external pull-up resistors on the unused inputs, and flow-through architecture lets designers optimize pc board layouts.

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