Designers building telecom and datacom equipment crave PCI expansion slots. In their minds, more slots mean more line interface cards for their systems. The PCI bus, while restricted in the number of expansion slots it can support, can be easily expanded with one or more PCI-to-PCI bridge chips. The only problem is that standard bridge chips can limit a system's performance.
To address this performance issue, Pericom Semiconductor has come up with a new kind of bridge chip. Instead of designing just another two-port bridge like its competitors, the company decided to add some value. The result was the PI7C7100—a triple-port PCI-to-PCI bridge that integrates two PCI-to-PCI bridges into a single bridge device.
There are definite advantages to having an integrated three-port bridge system rather than two separate dual-port bridges. For example, only one package is needed as opposed to two, saving board real estate. Another bonus is that there's less routing involved. The main benefit, however, is performance (Fig. 1). Here's why.
Consider a system with two bridges. Bridge one connects to secondary bus one and bridge two connects to secondary bus two. Now suppose there are devices on each bus and they want to communicate with one another. A lot of traffic moves from bus one up through the bridge to system memory, which is used as a buffer. From there, data travels back down the primary bus, through the second PCI bridge, and then onto secondary bus two.
It's evident that a lot of traffic goes back and forth unnecessarily on the primary bus just to get the two devices to communicate. To alleviate this, the PI7C7100 offers more than just bus expansion. It also provides a direct link from secondary bus one to bus two through the chip.
In other words, if devices on secondary buses one and two want to communicate, they can do so directly. Avoiding traffic on the primary bus is a performance benefit realized by the new architecture.
The chip is not designed for traditional PCs. In a typical consumer PC, the northbridge chip has enough drive capacity to handle the number of slots needed. Therefore, Pericom is targeting the industrial PC area, which means the server and router markets. These require more and more PCI bridges, due to the fact that most adapters are designed to work with the PCI bus.
Pericom is also focusing on CompactPCI, since this is the platform of choice for the telecom market. The company expects the PI7C7100 to find its way onto CompactPCI CPU cards. Containing a CPU and memory, these cards use a bridge chip to drive the other cards on the passive backplane. The bridge is used as an isolation or extra driver specifically for the slots.
In telecommunications applications, line-interface cards would be connected to the passive backplane (Fig. 1, again). With the exception of the line cards, all components would reside on a single CPU card. On the edge connector of the card are the CompactPCI connectors. The bridge chip interfaces to these and basically provides a buffer between the CPU card and the passive backplane. It's responsible for driving the backplane connectors as well.
Pericom is also targeting proprietary router designs, such as those developed by Cisco, Nortel, Ericcson, and others. These companies leverage existing PCI adapter cards for communications and storage. Another application area is video servers. Manufacturers of these systems generally leverage the market's large number of PCI VGA cards.
A glance at the block diagram of the PI7C7100 indicates the important configuration registers A and B (Fig. 2). These two registers provide a multifunction or dual-function device with space to accommodate the two secondary PCI buses.
The transaction queue and buffers have a rather deep FIFO architecture, with 256 bytes on the writes and 128 bytes on the reads. There are two sets of each to enable concurrent operation. This is useful for cases in which a device on secondary bus two wants to talk to a device on secondary bus one. Data goes through this FIFO to accommodate any device latencies.
Direct Connection Between Buses
Communication between the two secondary buses exists as a direct connection and can be compared to the operation of a switch fabric. The chip provides the equivalent of a point-to-point connection. In between are the FIFOs, which act as buffers and ensure that a link is established between the secondary one and secondary two buses.
The chip supports up to eight masters per secondary bus for a total of 16 masters. If there are two devices on secondary bus two, they can easily talk to each other. If the devices are on separate buses, a direct link is established. Therefore, it's as if both devices are on the same secondary bus.
The PI7C7100 is an 0.35-µm CMOS device that is fully compliant with the 32-bit, 33-MHz implementation of the PCI Local Bus Specification, Revision 2.1. It supports synchronous bus transactions between devices on the primary 33-MHz bus and the secondary buses operating at 33 MHz. The primary and secondary buses can also operate in the concurrent mode, which increases system performance. Concurrent bus operation offloads and isolates unnecessary traffic from the primary bus. In addition, all three ports meet the PCI-to-PCI Bridge Architecture Specification, Revision 1.0.
As for software support, most BIOSs can recognize and properly configure a standard PCI-to-PCI bridge. As this device adheres to the PCI bridge architecture specification, most BIOSs will know how to program it. When a BIOS does enumeration, it will see this device as two bridges and automatically configure it as if it were two separate PCI-to-PCI bridges. If this were to happen, the device would behave as two separate bridges. Everything would function properly, except for the overhead of traffic on the primary bus.
For the device to work as designed, a software driver is needed to program the registers in the chip. This driver sets the addresses from one expansion board to the other on the two secondary ports. It also establishes the direct link mentioned earlier. In other words, a special driver is required to take advantage of this feature.
For telecom, video-server, and similar applications, 33 MHz and 32 bits are presumed sufficient. But the trend is to aggregate all these channels into a single high-performance one. This would require higher-performance bridges. Pericom's plans call for a three-port bridge device that contains a 66-MHz, 64-bit primary bus as well as 66-MHz, 64-bit secondary buses. The company has already defined this and is working on releasing it in the fourth quarter.
Price & Availability
The PI7C7100 is available now in a 256-pin plastic BGA package. Pricing is $30 each in 1000-unit quantities.
Pericom Semiconductor Corp., 2380 Bering Dr., San Jose, CA 95131; (800) 435-2336; [email protected]; Internet: www.pericom.com.