Highly compact high-density EDO DRAMs have been created by integrating two die into an 89-pin ball grid array (BGA) package. Using a non-stacked approach with the dice, the 128-Mbit DRAM BGA memories measure a mere 1.55 mm high, some 1.04 mm shorter than an equivalent density device using stacked TSOPs. They also offer board real estate savings of 47%.Available organized as 16M x 8 (part number WPD16M8V-XB2C) or 8M x 16 (WPD8M16V-XB2C), the DRAM BGAs are also useful as building blocks for SO-DIMMs. For example, eight of the BGAs can be surface-mounted on a dual-sided, 144-pin SO-DIMM to create a 128-Mbyte module standing only 1" high. The DRAMs operate on 3.3V in either fast page mode (FPM) or extended data out (EDO) operation. They also have access times of 50 or 60 ns and 4K or 8K refresh cycles. The firm is also sampling a synchronous DRAM version of the device.
Company: WHITE ELECTRONIC DESIGNS CORP.
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