Vector Processing System Squeezes In 238 Million FPGAs

Featuring up to 238 million Xilinx Virtex II FPGA system gates, the Dream Catcher FPGA-based vector processor system offers I/O bandwidth reaching 65.1 Gbytes/s. Dream Catcher is a web of up to seven Dream Catcher nodes residing in a VME 64x chassis. Each node has one Wildstar II processing board with up to three Virtex II 8000-6 FPGAs, as well as a Wildstar Data Port (WSDP) I/O daughtercard supplying six WSDP connections and a Virtex 2000E-8 FPGA. A Quad Fibre Channel 2 I/O daughtercard supplies four full-duplex Fibre Channel 2 connections. The Fibre Channel 2 connections can link to a switched fabric, to a JBOD through an arbitrated loop, or to a RAID via point-to-point. Each node supports Dual Race++ as well as one Ethernet connection. All nodes have six WSDP ports and 38-pin connectors, which support up to 1.2 Gbytes/s per connector over up to 10 feet of coax cable. These connectors provide the mesh between the seven Dream Catcher nodes. The total processing power per node is up to 34 million gates, and the total I/O bandwidth per node is up to 9.3 Gbytes/s. Complete with Virtex II 8000-6 FPGAs, the Dream Catcher system costs between $1 million and $1.5 million. A more basic version, with Virtex II 6000-5 FPGAs on a Fibre Channel board, costs about $520,000.