When you write about technology on a full-time basis, it's sometimes difficult to keep a clear and unbiased perspective. This is hardly surprising, as most editors are inundated with pitches from companies that are trying to put their best foot forward. A good writer must act as a filter for his or her audience, revealing the facts and trends instead of merely repeating the hype. This is not always an easy task.
I was reminded of the importance of writing for my audience during the recent Design Automation Conference (DAC). A fellow editor (thanks, Jergen), who writes frequently for many of Europe's better technology publications, challenged me with a very simple question: What was the essence of this year's DAC? The answer he wanted was not from the perspective of the exhibitors or the EDA industry. Instead, it was from the viewpoint of the engineers and managers who are developing electronic products with EDA tools. His words reminded me of the responsibility that every editor has to his or her audience. From that point on, I saw things in a different light. For my engineering brethren, a report follows on the essence of DAC '03:
ASIC designs have reached maturity. This observation was reinforced by several studies that I will cover shortly. But it also was evident from walking the exhibit floor and looking at the products being offered. While the big EDA vendors offer improvements in their existing ASIC tool suites, many smaller tool vendors and startups were focused on FPGA and ASSP designs.
Are ASIC designs dead? This is certainly not the case. In fact, the emphasis of most of the technical papers and panel discussions was on low power, signal integrity, and system-level design issues for ASICs. Several papers also addressed nanotechnology design. After all, many ASIC designs for mobile products are already taking place at the 130-nm level.
If ASIC developments are leveling off, what designs are still climbing in terms of design starts? The Gartner Dataquest study found that FPGAs and ASSPs will be the leading design activities for many years to come. This is good news for the engineers and managers who work on design teams. I saw proof of this trend in many new products and existing product upgrades at DAC. You will see these products covered in upcoming issues of WSD magazine.
Another interesting observation that I gleaned from DAC was that few companies plan to invest large sums in EDA tools—at least for the foreseeable future. This was the finding of a study presented at the EDA Business Forum. While design starts are increasing, EDA tool budgets are declining. Is this bad news for tool vendors? Not necessarily. The study did suggest an increase in the sales of tools, which provide incremental value to the existing chip and board design flow. This observation tracks well with the "word from the street," which says that designers want tools that help them squeeze every bit of performance and power management from new and existing designs.
Design tools are a prerequisite to handling the ever-increasing complexity of ASIC, ASSP, and FPGA designs. To drive the ever-increasing cost of tool suites, however, vendors can no longer count on the relentless pursuit of Moore's Law. For the most part, revenues will have to come from improving existing tools and expanding coverage to FPGA and ASSP designs. In fact, the EDA Business Forum's study concluded that FPGA-synthesis tool usage would increase by 16% from last year. Signal-integrity analysis and power-/EMI-/thermal-analysis tool usage also is predicted to rise significantly in 2003.
Tracking nicely with this year's increase in FPGA tool usage was the continued growth of all FPGA tools. For example, the EDA Business Forum predicted an increase of 7% for FPGA place-and-route tools in the next two years.
What will bring the EDA community out of its doldrums? Few believe that it will be nanotechnology. Hope lies in improving the performance and profitability of existing and near-horizon technologies. Nanotechnology is coming, but it will not be mainstream for some time.
The essential message from DAC was both encouraging and cautionary: Things won't get worse, but they won't get much better. Don't wait for the next generation of EDA tools and designs. Instead, focus on improving the power, overall performance, and cost value of near-term products. There is still much to be gained from the 'last mile' of current EDA tools and services.
Please share your thoughts with us and our readers. Send your comments to me at [email protected].