Clean bits. That’s what strategic marketing manager Jon Hall of Analog Devices says that designers really want out of an analog-to-digital converter (ADC) for wireless and test equipment applications. It isn’t easy to get noise-free bits using a 16-bit ADC, especially at a 250-Msample/s conversion rate.
But that’s what you get with the Analog Devices AD9467, which has a spurious-free dynamic range (SFDR) of up to 100 dBF and a signal-to-noise ratio (SNR) of 76.4 dBFS. Its jitter is a low 60 fs rms, and its maximum bandwidth is 300 MHz with an input voltage span of 2.5 V p-p. The ADC’s programmable full-scale input range permits tradeoffs between SNR and SFDR.
Also, the AD9467’s on-chip input buffer is optimized for the highest effective number of bits (ENOB). This buffer can be adjusted for IF optimization of SFDR. The chip configuration and control is via a serial peripheral interface (SPI) port. And, its most amazing spec is the power consumption for an ADC of this speed, which is a low 1.35 W.
The ADC’s target applications mostly are related to wireless, especially cellular infrastructure. Its high dynamic range over a broad signal bandwidth enables software-defined radios for use with multiple standards such as LTE/HSPA/WCDMA, MC-GSM (class 1), and CDMA.
Furthermore, the AD9467 can be used with radar systems to improve their sensitivity and ability to acquire and track smaller targets with better accuracy. Test equipment manufacturers who live or die by their ADCs also will find the AD9467 a good choice for spectrum analyzers and other wireless gear.
The AD9467 comes in 250- and 200-Msample/s versions with a 10- by 10-mm, 72-pin lead-frame chip-scale package (LF-CSP) and 3.3- and 1.8-V supply voltages. The 250-Msample/s version costs $120 and the 200-Msample version is $100, both in 1000-unit lots. Analog Devices offers a full collection of support software and documentation, plus an evaluation board with a reference design. Samples are available now, with full production in November.