Digital communications equipment based on coherent detection need receivers that can generate a carrier synchronized signal from a suppressed carrier transmission. For example, in a two-phase carrier receiver such as BPSK, a common solution is to use a 2nd-order law device. If its input is a tone of frequency f0 with information in the phase Φ, its output is given by:
This signal is passed through a PLL that operates as a narrow-band bandpass filter around the frequency 2f0. Hence, if Φ = 0, the output phase also is 0. And if Φ = 180°, the output phase is 2 × 180° = 360° = 0°. Therefore, phase discontinuities are removed, and the PLL output is a continuous phase signal of frequency 2f0, where phase modulation has been eliminated. Then, a divider by 2 is sufficient to have a carrier synchronized with the received modulated signal. The same applies when using 4th-law devices with quadrature-carrier receivers, such as QPSK or QAM.
With this solution, we have a single phase, but its value can’t be guaranteed. For example, in a BPSK transmission, it can be stated that the PLL output is a synchronized carrier of frequency f0, but there’s no way of knowing whether the relative phase is 0° or 180°. A mistake in the relative phase can result in unexpected changes of the received “zeros” or “ones,” and vice versa. A block diagram depicts the carrier recovering process and the demodulator for a BPSK modulated signal (Fig. 1). The automatic phase detector is shown in the dashed lines.
In non-differential encoding, a phase reference adjustment is required to avoid false decoding. The usual solution is to transmit a known preamble at the start of some messages to permit phase adjustment. This is a good solution, albeit time-consuming in terms of preamble synchronization (training process). The approach presented is an alternative to phase discrimination based on the parity error bit of the UART. This alternative is useful in asynchronous phase communications and requires no preambles between the transmitter and the receiver. The circuit is based on the HD-6402 IC, which permits hardware detection of the parity error (Fig. 2).
The circuit operates on the principle that the correct phase reference permits a correct demodulation and, consequently, minimizes (and ideally, nullifies) reception errors. Incorrect phase references increase errors and, consequently, the number and the frequency of pulses in the parity error (PE) pin in the UART. The low-pass RaCa filter after the PE output gives a voltage value proportional to the number of errors, much like a voltage-to-frequency converter.
If this voltage is sufficient to activate the analog comparator (TL082 op-ampbased), the binary counter (4520) modifies their outputs. These outputs select, through the multiplexer (4052), one of the four phase references (0°, 90°, 180°, and 270°) given by the shift register (4015), whose outputs QA through QD are shifted versions of the recovered carrier. This system runs continuously like a tracking loop, until the correct phase reference is presented to the demodulator. At this moment parity errors are scarce, and a low voltage is presented to the analog comparator. This stops the phase tracking, and the system remains in the correct phase reference.
If some disturbance in the communication system produces new phase errors, the automatic phase-recovering loop runs again, searching for the correct reference.
The time constant of the RaCa filter and the comparator level (P1) are calibrated according to transmission speed. At 100 kbits/s, their values are Ra = 1 kΩ, Ca = 2.2 nF, and P1 ≈ 500 Ω. The loop clock is 666 kHz. Microswitches are added to enable manual phase selection. SW1 inhibits the automatic phase detector, and SW2 and SW3 select the phase reference.