Electronic Design
Chips Make Software Defined Networking Work

Chips Make Software Defined Networking Work

Software defined networking (SDN) and network function virtualization (NFV) are changing the enterprise landscape. NFV relies on virtualization support within servers but SDN requires changes in the switches. Broadcom and Cavium are delivering new chips that target data center SDN. They are designed to deliver 3.2 Tbits/s of bandwidth. They deliver up to 32 ports of 100G Ethernet using 25 Gbit/s SERDES. They also support different port configurations that include 10G, 25G, 40G, and 50G ports.

Cavium’s XPliant Ethernet Switch family supports the XPliant Packet Architecture (XPA). XPA consists of five major functions (Fig. 1) including parsing, lookup, packet modification, queueing and counter/instrumentation. All functions are customizable. Profiles define how primitive operations are used. This approach significantly reduces the design cycle for handing new functionality.

Figure 1. Cavium’s XPliant XPliant Packet Architecture (XPA) supports all major protocols as well as customization to handle future standards.

XPA can handle OpenFlow 1.3 and the forthcoming OpenFlow 2.0. This includes support for table type patterns (TTP) for forwarding that will be part of OpenFlow 2.0. It provides a more abstract view versus the conventional match/action table approach to packet processing. OpenFlow 2.0

It handles standard SDN protocols and tunnels like VXLAN and NVGRE as well as custom protocols. This allows it to address future standards such as GENEVE.

XPA does not incorporate any on-chip cores. It is designed to handle L2 and L3 tasks. Typically higher level protocols and functions would be addressed by NFV.

Cavium’s components can be used for a top-of-rack (ToR) leaf or spine switches. Its profile configuration could allow a single switch to be reconfigured for either chore reducing the number of device types within a data center. It also provides a way for vendors to differentiate their switches by incorporating additional functionality.

Cavium is delivering a range of chips. The largest is the CNX88091 that supports 32 ports of 100G Ethernet.

Broadcom’s StrataXGS Tomahawk Series has very similar specs and it also targets the L2/L3 SDN space. It has a configurable pipeline with sub-400 ns latency port-to-port. Broadcom’s high-density, flow processing is called FleXGS. It has configurable forwarding/match/action capabilities.

StrataXGS supports standard protocols such as high performance storage/RDMA protocols including RoCE and RoCEv2. It also supports OpenFlow 1.3+ using Broadcom’s OF-DPA. Its flexible policy enforcement is designed to handle new virtualization protocols.

Broadcom includes a number of technologiessuch as Enhanced Smart-Hash load balancing modes to avoid leaf-spine congestion. Its Smart-Buffer technology is designed to provide five times the performance compared to static buffering found in some of their earlier parts.

The StrataXGS handles single-chip and multi-chip HiGig solutions for ToR and spine switches. HiGig is Broadcom’s interface designed to interconnect up to 32 chips.

The solutions from Broadcom and Cavium will be changing the way the data center works. They provide significantly better health and monitoring capabilities in addition to the higher bandwidth and increased functionality. This will make management and troubleshooting of large networks significantly easier. Their customizability should significantly extend the life of a switch as current switches often need to be replaced or upgraded to handle new protocols.

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