Electronicdesign Com Products Communications Chipset Designed Using Scalable Non Blocking Sts 1
Electronicdesign Com Products Communications Chipset Designed Using Scalable Non Blocking Sts 1
Electronicdesign Com Products Communications Chipset Designed Using Scalable Non Blocking Sts 1
Electronicdesign Com Products Communications Chipset Designed Using Scalable Non Blocking Sts 1
Electronicdesign Com Products Communications Chipset Designed Using Scalable Non Blocking Sts 1

Chipset Designed Using Scalable Non-Blocking STS-1/AU-3 Architecture

Aug. 1, 2002
Claiming to set new benchmarks for aggregating, grooming and transporting 2.5-Gb/s and 10-Gb/s metro services, the CHESS-III chipset includes the PM5376 TSE-Nx160 STS-1/AU-3 cross-connect device and PM5326 ARROW-2x192 and PM5324 ARROW-1x192 SONET/SDH

Claiming to set new benchmarks for aggregating, grooming and transporting 2.5-Gb/s and 10-Gb/s metro services, the CHESS-III chipset includes the PM5376 TSE-Nx160 STS-1/AU-3 cross-connect device and PM5326 ARROW-2x192 and PM5324 ARROW-1x192 SONET/SDH framers. The TSE-Nx160 device grooms sub-wavelength traffic and is claimed as the industry’s first non-blocking, scalable STS-1/AU-3 cross-connect. Its architecture enables metropolitan transport equipment to scale from 160 to 640 Gb and provides 2.5-Gb/s and 622-Mb/s I/O support for new and legacy line cards. The ARROW-2x192 and ARROW-1x192 are touted as having the highest density OC-48/STM-16 and OC-192/STM-64 transport available with the latest SONET/SDH transport features for both current and next generation metropolitan networks. Available in FCBGA packages, single-unit prices are $1,725 for PM5376 TSE-Nx160 STS-1/AU-3, $1,295 for PM5326 ARROW-2x192, and $840 for PM5324 ARROW-1x192. For more details, contact PMC-SIERRA, Santa Clara, CA. (408) 239-8000.

Company: PMC-SIERRA

Product URL: Click here for more information

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