Radio-powered ICs have evolved from the earliest RFID devices to processor-driven transaction processors capable of handling complex operations such as security encryption and financial transactions. The latest trend is the adoption of near field communications (NFC) techniques to position smartphones and other mobile devices as electronic wallets. Examining a second-generation NFC chip shows how developers are providing flexibility for this emerging market.
Emerging NFC standards call for three modes of operation, depending on application. One mode is for contactless card emulation, where the NFC device activates only when interrogated by a reader and draws its power from the reader. In the second mode the NFC device is itself the reader for a passive RFID tag. The third mode is peer-to-peer communications between two NFC devices.
Along with offering one or more of these operating modes, NFC devices need to support at least one of several design-dependent interfaces. These include the host controller interface (HCI) for USB, the single wire protocol (SWP) for connection to a SIM card, and the European Telecommunications Standards Institute smart card platform (ETSI/SCP) interface. To give designers maximum flexibility an NFC chip would offer all of these options.
The first-generation NFC chips that we explored were narrowly targeted, implementing only single interface options. The second-generation NXP-tPN544V1D NFC chip (Fig. 1) shows that vendors are now providing more flexibility for their customers. The chip supports a variety of operating modes and interfaces, using a creative approach to help minimize power consumption.
The PN544 is a sophisticated device fabricated using a five-metal-layer, 180nm CMOS technology and incorporates an extensive analog section. The design consists of five major blocks:
- Power management unit (PMU)
- Processor, memory and clocking
- Multiple data interfaces
There are several major features of interest. The interface sections, for instance, include all of the major data interface standards needed in an NFC chip. The clocking section includes a substantial fractional digital phase lock loop (DPLL) to generate the multitude of different frequencies the various interfaces require.
The chip’s power design, however, is one of its most significant features. Among the analog circuits the chip includes a power-by-field block grouped with and connected to the transmitter section. This block gives the chip the option of either using the mobile device’s system power or being powered solely by the RF field of an interrogating device. The transmitter and power-by-field blocks are designed to connect to external electromagnetic compatibility filters and impedance matching devices, and the transmitter is configured to generate and modulate a carrier signal. Thus, the chip can operate in all three standard NFC modes, including card emulation when the device is turned off.
In conjunction with the power-by-field block, the PN544 has a flexible power management unit (PMU). This PMU ensures that the device gets regulated power and is responsible for making the entire chip power efficient. There are independent low dropout (LDO) voltage regulators for each of the data interfaces as well as for the transmitter. Each of the regulators has its own power feed from the PMU, and each section is on an independent section of the power plane. Thus, the PMU is able to selectively power only the circuitry needed for the specific operating mode and data interface that the application requires. When activated, the NFC chip is able to determine which interfaces and protocols a given transaction requires and avoid wasting even standby power in the unnecessary circuitry.
The chip is fairly large, measuring 3.1mm by 3.1mm. The PN544, therefore, has traded die area for flexibility. By offering developers a full selection of operational and interface options while using segmented power planes to minimize consumption, this second-generation NFC chip gives mobile device designers the flexibility they need.