Electronic Design

Counter Demodulates Narrowband FSK Without Synchronization

Frequency shift keying (FSK) is a popular digital modulation technique for data transmission. Some common applications of FSK modulation include both wired and wireless data transmission as well as infrared remote controls for consumer electronic equipment.

FSK demodulation can be either coherent or noncoherent. Coherent detection always demands carrier and bit synchronization, typically achieved using phase-locked loops (PLLs). PLLs are very noise-sensitive and normally call for a trimming adjustment inside the loop filter.

FSK noncoherent demodulation can be implemented with two bandpass filters and two envelope detectors. Bit synchronization may be required as well. In narrowband FSK transmission systems, bandpass filters must have a very high quality factor, making implementation more complex.

This idea presents a noncoherent, narrowband FSK receiver that eliminates the drawbacks mentioned above. Figure 1 shows the FSK demodulation circuitry in which neither PLLs nor high-quality-factor bandpass filters are used. With this high-frequency (HF) demodulation circuit, no trimming adjustments are necessary.

L1, L2, C4, and C7 form two resonant circuits, implementing an input filter whose passband is centered at 10 MHz. A differential high-frequency amplifier amplifies the 10-MHz signal. IC1 and IC2 combine to make an automatic gain-control (AGC) circuit. The amplified signal is then converted into a digital waveform by a wideband comparator, IC3. The resulting digital signal clocks a 4-bit counter (IC4). Oscillator IC5 clears the counter. IC6A, the D-type flip-flop, latches the counter's most significant bit at the rising edge of the oscillator signal OSC_OUT. Since the oscillator circuit generates a 50% digital waveform duty cycle and the two FSK frequencies are:

f1 = 9.83 × 106 Hz      (bit "0")

f2 = 10 × 106 Hz        (bit "1")

the desired oscillator frequency for IC5 is calculated as:

The calculated OSC_OUT frequency also can be divided or multiplied by a power of two. Counter IC4 counts only during the low period of the oscillation cycle. To clear the counter, the OSC_OUT signal's remaining high period is used. IC5 can be implemented using a crystal oscillator module, a TLC555 in an astable configuration, or an oscillator circuit powered by a quartz crystal and a 74HCT02 IC.

Resistors R10 and R11 should have values equal to the HF_IN source impedance. For instance, if this FSK receiver is connected to a 50-Ω cable, then R10 and R11 should be 50-Ω resistors. This selection will provide maximum power transfer. Once diode D1 rectifies amplifier IC1's output voltage, the resulting dc voltage is amplified and inverted by IC2A.

Differential amplifier IC2B inverts IC2A's output voltage, producing a positive AGC voltage signal. IC2B also adds the REF voltage, which is scaled by resistors R1 and R4. The differential voltage amplification is then equal to 40 + 25(VREF −VAGC), with VREF = 1.4 V. IC3 receives the AGC-system output signal and converts it into a TTL-compatible signal to drive the IC4 clock.

To provide the negative supply voltage required by the AGC system, a MAX660 is used to generate a −5-V supply voltage from the 5-V single-supply voltage.

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