Electronic Design

Digital Technique Improves Jitter Measurement

Jitter has always been a problem in high-speed data communications systems. As speeds increase to 10 Gbits/s and beyond, measuring jitter is becoming more and more challenging. So, Tektronix has developed a new and better method of jitter measurement. Known as digital jitter analysis (DJA), this patent-pending method is faster, simpler, and far more accurate than even the latest traditional analog techniques.

A fast reference oscillator operating at 2n power times the baud rate drives an n-bit counter. Assuming a 2.5-Gbit/s signal with a bit time of 400 ps and a 5-bit counter, this translates to a reference frequency of 32 × 2.5 = 80 GHz. With this arrangement, the counter cycles through its full range once every baud period (see the figure, a).

The counter output is fed to a register where the value can be latched. The register is driven by the signal whose jitter is to be measured. When a leading or trailing edge occurs, the current counter value is latched into the register. The stored value represents the phase of the edge within the unit interval, or UI (jitter is measured in peak-to-peak rms and percent of the UI). The circuit then "time stamps" each NRZ edge with a binary number where the LSB weight—2−n UIs—is the resolution.

These n-bit phase numbers are then extended to N-bit numbers to prevent the overflow that occurs in going from one bit interval to the next. The bit extender subtracts the previous value of the counter from the current value, producing a difference value. The sign bit of the difference is extended, in this case to 17 bits. The resulting extended numbers are accumulated, effectively reversing the effect of the difference circuit. But now, the numbers are many bits longer. The 17-bit numbers are then digitally filtered. This low-pass function averages the values and provides an extra two bits of resolution.

To measure jitter in gigabit-rate signals, the reference clock must be many times higher in frequency, making this a difficult requirement. The 80-Gbit/s clock in the example above isn't actually used. Instead, the high-frequency clock and the 5-bit binary counter are replaced by a 1.25-GHz clock followed by a delay line with 32 taps (see the figure, b).

The delay line outputs are latched into the register as the value representing the edge trigger time. The nonstandard code produced by the delay line is converted to standard binary numbers by a binary coder to simplify processing in the bit extender. The resulting 5-bit numbers are then extended and filtered as described earlier. With this arrangement, the resolution is 1/128 UI (3 ps) over a 4096-UI peak-to-peak range for signals up to 10 Gbits/s.

This new technique offers the advantages of immunity to noise, repeatability, a wider dynamic range, and a wide frequency range. It's expected to help in designs of 1- and 10-Gbit/s Ethernets, as well as OC-48 and OC-192 Sonet systems with DWDM, where jitter has become a major focus as timing margins have decreased.

While Tektronix hasn't yet an-nounced a product using this technique, you can no doubt expect to see something in the very near future. For more information, call (503) 627-7111 or go to www.tektronix.com.

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