Electronic Design

The Elusive Software-Defined Radio

Will SDR become the ubiquitous wireless method, or is it destined to fall into the "niche technology" category?

Software-defined radio (SDR) represents the future for some wireless technologies, but it's still a work in progress. Like any technology, it's followed an evolutionary path as components and practices continue to improve. Its adoption is more widespread, too, as chips track Moore's law and as better software comes along.

SDR is a moving target. Its current "reality" is relatively small today, but its definition and place in the industry continues to evolve. Cell phone basestations and military radios are just the onset of an SDR movement that will grow as needs and opportunities are identified and as electronic and software technology permit.

WHAT IS SDR?
In the beginning of any new technology, definitions are a bit fuzzy until we see real products and applications. While the term SDR is still subject to interpretation, though, the industry is gradually settling on some concrete definitions. Early on, SDR was broadly defined as "any radio that used software to perform modulation and demodulation." Using that definition, a huge population of existing radios like cell phones, basestations, and wireless local-area networks (WLANs) qualifies as SDR.

In any case, SDRs are digital radios that attempt to complete as much of the signal processing—digitally—on both the transmit and receive sides of a wireless application. Most times, this involves a programmed processor, such as a general-purpose processor (e.g., an embedded controller or digital signal processor).

The SDR Forum, an organization dedicated to advancing the development and deployment of SDR, has a formal definition of SDR that includes five tiers:

  • Tier 0: A digital hardware radio that cannot be altered
  • Tier 1: Software-controlled radio (SCR); software can change some functions like power level and interconnects, but not modulation or frequency of operation
  • Tier 2: Software control of modulation, wide/narrow band, security, waveform generation and detection, but mostly frequency constrained
  • Tier 3: Ideal software radio (ISR); elimination of any downconversion or upconversion in reception or transmission; full programmability
  • Tier 4: Ultimate software radio (USR): fully programmable but able to support a broad range of frequencies and functions concurrently (two-way, GPS, video, smartcard, satellite, etc.).

Even these definitions are subject to interpretation, and the SDR Forum admits that it's updating and revising them. Nevertheless, they offer the big picture. In general, the end point is to get SDR to the point where it's completely flexible in terms of defined operational standards and independence of operating frequency.

Cell phones and basestations qualify under the Tier 0 and 1 definitions. So do some WLANs. However, real SDR isn't widely used yet—except in the military, where R&D teams have made great strides in creating an effective, and reasonably sized and priced, SDR.

The military's Joint Tactical Radio System (JTRS) project's goal is to build a group of compatible radios that operate from 2 MHz to 2 GHz with complete frequency agility. They also must be able to adapt to any modulation or protocol. Prototypes were built and tested, but final units haven't reached widespread adoption to this point.

An ideal SDR digitally codes and modulates the data that's going to be communicated in a baseband processor before transmitting it (Fig. 1). Next, the SDR sends the data to a digital-to-analog converter (DAC) and then to a power amplifier (PA), where it finally reaches the antenna.

On the receive side, the signal picked up by the antenna is fed to a low-noise amplifier (LNA), where it's boosted to a level that can be handled by an analog-to-digital converter (ADC). The digital output of the ADC is then processed, as necessary, in a baseband processor to recover the originally transmitted signal.

While it's possible to realize an ideal SDR at low frequencies, most wireless activity is above the VHF and UHF ranges and well into the microwave region. That's why most of today's SDRs use mixers in the front end to perform analog upconversion and downconversion (Fig. 2).

On receive, a mixer downconverts the signal to achieve an intermediate frequency (IF) that can be handled by today's ADCs. An upconvert mixer takes the DAC signal to be transmitted and converts it to the final transmission frequency. The I/Q mixer format preserves phase and frequency information contained in most digital modulation schemes.

Digital downconverters (DDCs) are commonly used after the ADC to further lower the data rate so that memory requirements may be relaxed and processing speeds are more moderate. Digital upconversion (DUC), used at the transmitter, takes a lower set of frequencies and boosts them up to an IF that's closer to the transmit frequency. These devices come as individual ICs, but their functions also can be implemented in the baseband processor.

A DDC does what an analog downconvert mixer does, but in a digital manner. It takes the ADC samples and multiplies them by samples of the carrier frequency generated by a numerically controlled oscillator (NCO) or direct digital synthesizer (DDS). Multiplying is the same as mixing. Multiplying the signal by a carrier frequency produces signals that are the sum and difference of the signal and local oscillator frequencies.

The difference signal is the intermediate frequency (IF) that contains the baseband information. The higher-frequency sum signal is filtered out. Next, the resulting signals are decimated, meaning that only one of each N samples is retained and the others are discarded. This lowers the sample rate, making it far easier to process the data in a DSP or FPGA. Digital upconversion is a similar process in reverse. DDC and DUC are a part of almost all modern SDRs.

The baseband processors may be fast standard processors like those in a PC or laptop. More often, though, they're programmable DSPs. In some cases, an FPGA is used. Modern SDRs typically use both a DSP and an FPGA, with the processing duties divided up as appropriate to the capabilities of each.

SDR's overall goal is to have ADCs and DACs that are fast enough to eliminate the conversions so that all processing (filtering, modulation/ demodulation, forward error correction, etc.) is performed digitally. Unfortunately, we aren't there yet.

But it is possible to build a multiband, multimode, multifunction, multiprotocol SDR that can be quickly reprogrammed to handle a wide range of applications. By reprogramming the hardware with new code, the radio can change its nature and be used as needed.

Designers of SDRs want reconfigurability with minimum latency and wide-ranging flexibility. Such a radio can handle many "waveforms." In SDR lingo, a waveform is simply all of the software that defines the air interface, protocol, and so on for a specific standard.

COGNITIVE RADIO
Some researchers are going one step further with the dynamic programming capability by developing an even more capable SDR—the cognitive radio (CR). Some researchers tend to view CR as just an extension of SDR, while others believe that CR is a superset of SDR.

In any case, CR is a smart or intelligent radio that has complete self-awareness of its abilities. It can also seek out other radio conditions and match them to achieve optimum communications. In essence, a CR is an SDR that's a fully reconfigurable radio—especially as one that's frequency-agile. A CR's objective is to take advantage of all unused spectrum space that exists for any given period of time.

Most wireless experts believe we're experiencing a spectrum crisis because nearly all of the usable spectrum has already been allocated by the FCC and other regulatory agencies in other countries. Despite that allocation, anywhere from 70% to 95% of the spectrum remains unused at any given time.

CR will be able to seek out and find usable spectrum and then adjust its protocol, modulation, and other features to take advantage of those blank areas. Of course, at present, it's easier said than done. That's why CR has yet to be fully developed. It's being widely studied in universities and the military continues to study it extensively, ultimately leading to a real product that takes advantage of the wide segments of available spectrum. The FCC fully blessed CR and outlined its ideas and policies in December 2003.

CR's key characteristics include location awareness, as well as the ability to sense its spectrum surroundings and learn. It additionally must know policies, rules, and regulations and then be flexible enough to reconfigure itself to, say, 10 or 12 different air interfaces or protocols.

A CR has artificial intelligence characteristics. Its knowledge comes in the form of a data/knowledge base that's expandable. Thanks to a reasoning capability, a CR can use that knowledge to do what is necessary with the available hardware and software to achieve some desired communication. Again, we aren't there yet, but the day will eventually arrive.

DESIGN ISSUES
Five key factors limit our ability to design a power-efficient, affordable SDR: ADC/DAC speeds and dynamic range, processor speeds, RF front-end limitations, software, and power consumption.

ADC sampling speeds continue to creep up as ICs shrink and new architectures are adapted. Today, ADCs offer sampling data rates of up to 250 to 300 Msamples/s. Off-the-shelf ADCs with 12- to 16-bit resolutions at these speeds are available, such as those from Analog Devices and Texas Instruments. If resolution isn't that critical, you can get sampling rates to 2 Gsamples/s with 8- to 10-bit devices from vendors like Atmel.

Tricks like using two or more ADCs in parallel and driving them with different phase clocks let designers multiply the data rate by the number of ADCs employed. Using two ADCs with this technique is called ping-ponging.

Keep in mind that the ADC doesn't just rely on the correct sampling rate. The other critical specification is dynamic range, usually expressed as spurious free dynamic range (SFDR). It defines the range between the peak noise floor and the signal peak. Common fast ADCs have SFDRs in the 70-to 90-dB range, but more is better.

If you really need high-octane sampling speeds, and cost or power aren't as big an issue, try the supercooled ADCs produced by Hypres Inc. These ADCs are contained in a small cryocooler that reduces their temperature to about 4.5 K. It's not quite absolute zero, but it's low enough to boost sampling rates well into the tens of gigasamples/s. Units running at 20 and 80 Gsamples/s with 12-bit resolution and more have been developed. The key element behind the success of these devices is a small low-cost cryocooler (Fig. 3).

With these very fast ADCs, designers can connect the antenna directly to the ADC. Supercooling the front end like this not only provides a high sampling speed, but also drastically lowers the noise figure. Then, the antenna sets the noise specification.

The potential for a sampling speed in excess of 100 Gsamples/s plus a demonstrated SFDR in excess of 100 dB seemingly ensures that the cryocooled ADC will find first use in military or space applications—where cost and size are less of an issue. Basestations represent another target.

The RF front end also is a consideration in most SDRs, especially wide-spectrum CRs. The front end usually consists of the LNAs, filters, transmit/receive (T/R) switches, and PAs. Since most radios are allocated to a specific frequency band, they incorporate input and output filters that reduce noise and minimize spurious transmissions.

With widening radio bandwidth and incorporation of frequency-agile techniques, developers must accommodate complex multiple input and output circuits. Good solutions for narrowband operation are well known, but as the band widens, the circuits at the antenna get muddled. Even multiple antennas may be necessary.

Another design consideration revolves around processing speed. Since SDRs must operate in real time, the pressure is really on the processor to keep up with the blizzard of data coming in from the ADC. Until now, standard commercial off-the-shelf (COTS) DSPs have been used for most applications. With DSP clock speeds reaching 1 GHz, they fill most needs.

But as the SDR grows in flexibility, it also becomes more complex. As a result, higher processing speeds are essential. A popular alternative today is FPGAs, with their super-high speeds, flexible reprogrammability, and multiply/add and accumulate (MAC) capability that lies at the heart of most DSP algorithms. For example, Xilinx's Virtex 4-SX FPGAs are optimized for SDR.

For some applications, though, FPGAs simply can't do it all. If floating-point math is necessary, a standard DSP is the only practical solution. Most new designs incorporate standard DSPs and FPGAs. Even multiple DSPs are used in certain designs. Partitioning of the software is based on the specific application.

In most cases, a super-fast embedded RISC controller also is put to work on some parts of the application. The processing speed that's needed for a given application is less than you would expect, since digital downconversion and decimation reduce it to a manageable level. Figure 4 illustrates the waveform processing section of a modern SDR.

A fourth issue is the software. While algorithms for most basic functions are available as plug-in modules or can be easily programmed, they all must work together. A real-time operating system (RTOS) is needed, along with some overlying software to coordinate and manage all of the other software.

Such a system is now available. Called the Software Communications Architecture (SCA), this software platform was developed under the military's JTRS project. SCA has been adopted as the basis for all future military SDRs, and it will greatly influence the development of a similar software platform for commercial products.

SCA is an open framework that helps ensure the portability, scalability, and reusability of the hardware and software in a SDR. It also helps achieve product interoperability. And, it pulls everything together, including the interfaces, board-support packages, an operating system, and middleware.

SCA also helps set up and tear down the various waveforms supported by the radio and coordinates all operations. Known as the Common Object Request Broker Architecture ( CORBA), the middleware facilitates intermodule communications.

Finally, power consumption is always an issue, though perhaps it's less of a problem in radios going into basestations, vehicles, or other places where there's resident power. Because of the high processing power and drain of other fast support circuits, SDRs really eat lots of watts. A watts/MIPS tradeoff is at the heart of most designs.

At this point, SDR isn't ready for cell-phone handsets or other really small battery-powered terminals. The military is working on this problem, though, as it creates its own handheld field radios. This problem eventually will be solved by a combination of semiconductor processing advances and clever design.

OTHER DESIGN CONSIDERATIONS
Designing an SDR from scratch is a real challenge. But to make the task easier, some companies already offer bundles of generic hardware and software to initiate experimentation and implementation.

Pentek's 7142 software radio module provides all you need to kick off an SDR project (Fig. 5). Basic specifications include four 14-bit, 125-Msample/s ADCs; 768 Mbytes of memory; dual Xilinx Virtex-4 FPGAs for DSP and interfaces; a 16-bit, 500-Msample/s DAC; and a sync bus that enables multiple board synchronization.

The 7142 comes in a variety of form factors (PCI, 3U and 6U Compact PCI) and configurations with software support tools. It's one of many Pentek SDR systems with a wide range of DSPs and general-purpose processors and operating systems.

National Instruments' PCI-5640R reconfigurable IF transceiver uses the Xilinx Virtex-II Pro FPGA and Lab-VIEW FPGA for communications system design and research in universities and industry. The 5640R is a two-channel IF input and two-channel IF output PCI board with 2 Mbytes of SRAM. ICs handle DDC and DUC, thereby offloading the FPGA.

Keep in mind that you won't get very far in your designs without a way to test and measure your system. Tektronix's AWG400 family of arbitrary waveform generators (AWGs) offers one way to test an SCA receiver. With the RSA6100A real-time spectrum analyzer, designers can test SDR transmitters at frequencies to 14 GHz, with a bandwidth up to 110 MHz and a SFDR of 73 dB (Fig. 6).

SDR isn't for every wireless application. It's even overkill for many simple wireless tasks. But it will gradually find its way into more commercial and consumer products. For now, it's a high-end technology that will greatly benefit satellite communications and a wide range of military needs—not only JTRS radios, but also signals intelligence (SIGINT) for the NSA, CIA and DIA, and electronic warfare (EW) equipment.

One big hope is that SDR will help solve the widespread incompatibility of the public safety, public service, and military radios that need to communicate during emergencies. Also anticipated is increased application in cellphone and broadband wireless basestations.

NEED MORE INFORMATION?

Analog Devices Inc.
www.analog.com
Federal Communications Commission
www.fcc.gov
Hypres Inc.
www.hypres.com
Joint Tactical Radio System (JTRS)
jtrs.army.mil
National Instruments
www.ni.com
Pentek Inc.
www.pentek.com
SDR Forum
www.sdr-forum.org
Tektronix Inc.
www.tektronix.com
Texas Instruments
www.ti.com
Xilinx
www.xilinx.com

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