By Sylvie Kadivar, Handoko Chendra, Robert Gruijl, and Dong Nguyen, NXP Semiconductors
The convergence of markets is driving the need to develop new interfaces but is also impacting the performance and features of existing interfaces. The most common of the latter is the Universal Asynchronous Receiver-Transmitter (UART), widely used for standard serial connectivity. UARTs can be used as a communication interface between a host processor, such as a microcontroller or embedded processor, and a peripheral. These standalone solutions are becoming attractive solutions in a broad variety of applications and markets ranging from industrial equipment to smartphones.
UARTs are the preferred communication interface among a given module (e.g. Bluetooth, GPS, RFID, high-port Ethernet servers) and the main processor or chipset. This is understandable since UARTs continue to be an efficient interface with minimum software overhead and complexity both from the application and software driver point of view. Despite the growing trend of more integration of UARTs in processors and chipsets, there will be tradeoffs that these key chips need to make to balance die size/cost versus performance and choice of peripherals. The implication of this is that processors and chipsets continue to find themselves short of ports. Thus standalone UARTs available in different form factors become a value-add to a given system.
The need for a new generation of highperformance UARTs is driven by several market dynamics including process and chipset trends and connectivity and peripheral trends. Connectivity and peripheral trends dictate the need for high-speed UARTs with flexible host interfaces operating at lower voltages with minimal power consumption and providing a high data rate that can satisfy new connectivity standards such as Bluetooth EDR.
The new generation of systems is designed using high-end processors that can execute a larger amount of tasks in a shorter period of time. These processors operate in the 3.3V, 2.5V or 1.8V range. With this in mind, even basic interfaces such as UARTs have to be designed to continue to further reduce CPU overhead. To create a high-performance UART, the following features must be considered: the nature of the host interface, the UARTs FIFO depth, baud rate, supply voltage and the power consumption. Other features can also provide significant advantages in a given design: low resolution clock prescaler, auto RS485 support and advanced packaging.
The Host Interface and Processing Time
The UART can be connected to the host either by a parallel or a serial bus. Currently, many of the standalone UARTs provide two types of 8-bit asynchronous memory interfaces, compatible to most Motorola and Intel bus interfaces. Some UARTs contain both interfaces such as the NXP Semiconductors SC28Lxx and the 1.8V SC16C85x family of UARTs. With the help of a configuration pin, the standalone UART can be set into a Motorola or Intel mode. In a number of handheld processors, a new interface known as VLIO (variable latency I/O) is also available and a new generation of 1.8V UARTs is being designed to enable a seamless link to the bus as shown in Figure 1.
The benefit of the parallel bus interface is its high throughput, which can go up to 100 Mbps. The drawback is that it requires around 15 wires to interface to the processors. To overcome this drawback, or eliminate the co-dependency on the parallel bus, some UARTs have the option to connect to the host via a standard serial bus such as SPI or I2C. A popular solution today is the NXP SC16IS7xx series that provides a seamless link to the host via an I2C or SPI port and reduces the 15-wire connection to the host to five (for I2C) and seven (for SPI) as shown in Figure 2. This serialized UART has the additional benefit of providing designers with an off-the-shelf I2C or SPI to RS232/RS485/IrDa protocol converter. The drawback is the serial bus speed is limited to 400 Kbps for I2C and 15 Mbps for SPI.
Once the host interface is selected, the optimization of the host processing time is dependent on the following features:
- UART's FIFO depth and FIFO counters
- number of interrupt trigger levels
- hardware and software flow control.
The FIFO depth of a UART directly influences the CPU load for the task of transferring data to or from the UART. The larger the FIFO depth, the more data can be transmitted or received per interrupt, thus contributing to less CPU interruptions. A standard FIFO depth is in the range of 16 to 64 bytes. However, more and more designs require UARTs with deeper FIFOs and a growing number of vendors are providing standalone solutions that can go up to 128 bytes. Today the UARTs with the deepest FIFOs in the market are the NXP SC28L202 and SC28L201 that have 256-byte FIFOs.
The following example illustrates the benefit of deeper FIFOs. Assume that the UART is set up to transfer data at 115.2 Kbps and the character format is 1 start bit, 8 data bits and 1 stop bit. This is a 10-bit character and at a 115.2 Kbps baud rate, it will take the UART about 86.8 µs to receive one complete character. If the UART receiver FIFO size is 16 bytes, then it will take approximately 1.39 ms (16 * 86.8 µs) to fill up the receiver FIFO. At this time the UART will generate a receive data ready interrupt to the host, and the host must immediately read the data in the receive FIFO or else an overrun of the receive FIFO will occur if another character is received by the UART. With the above set-up, the host will get an interrupt from the UART every 1.39 ms during receiving. But if the UART receive FIFO size is 128 bytes, then the UART interrupt interval is eight times longer (128 / 16 = 8) at 11.12 ms during receiving. With a 128-byte FIFO, the host services the UART once every 11.12 ms instead of 1.39 ms. The host processor can use the time saved to do other tasks.
In many applications today, the system needs to read a Line Status Register (LSR) of the UART to first find out if there is data in the receive FIFO. This requires the CPU to poll the LSR every time it reads a character from the receive FIFO. This increases the CPU processing time considerably. Only a limited number of standalone UARTs, such as the NXP SC28L202 and SC16C85x, have a FIFO counter that allows the CPU to find out the number of characters in the FIFO before retrieving the data. This approach eliminates the CPU from reading the LSR every time it reads the data from the RX FIFO and further contributes to system optimization.
Programmable Interrupt Trigger Levels
In some applications, a data packet with a fixed length needs to be received and responded to by the host within a fixed amount of time. By using the interrupt trigger level of a UART, designers can program the UART to generate an interrupt after it has received a given number of characters or when a given number of characters have been sent by the UART. Current integrated UART solutions have a number of predefined trigger levels such as 1, 4, 8 or 16. The drawback of the limited number of interrupt trigger levels is that the designer cannot easily program the UART to generate an interrupt after a data packet that is not 1, 4, 8 or 16 bytes. A UART such as the NXP SC16C850L/852L can provide 127 interrupt trigger levels thus giving the designer the flexibility to program the UART to set the interrupt trigger level to any byte between 1 and 127.
Hardware and Software Flow Control
Hardware and software flow control provides an automated handshaking mechanism between two communicating UARTs, relieving the CPU from the task of preventing data overflow in the UART FIFOs. Many integrated UARTs do not incorporate this feature, which is becoming critical in applications where a processor's bandwidth is limited and it does not have time to implement either hardware or software flow control. More and more standalone UARTs include this capability, providing designers with the additional benefit of relieving CPU workload.
The need for higher speed UARTs is becoming more and more critical. Current connectivity solutions such as Bluetooth require UARTs that can provide up to 3 Mbps speed at lower voltages. With the new generation of standalone UARTs, large amounts of data can be processed quickly and transferred at high speed while maintaining very high data integrity on all UART channels. Today a number of standalone UARTs offer data rates up to 5 Mbps at 3.3V, and a new generation of UARTs, such as the NXP SC16C85x family, will provide similar baud rates at 1.8V as shown in Figure 3. These kinds of UARTs provide a significant value added both in performance and time-to-market around a key chipset and overcome the limitations of 1 Mbps UARTs currently available in integrated solutions. In addition to higher speed, a number of standalone UARTs provide the designer with the capability to program the operating speed of the receiver and transmitter independently, which makes the standalone UART particularly attractive for applications such as highspeed clustered terminal systems and bridges.
UART Supply Voltage, Power Trends and Packaging With processors and chipsets migrating to lower supply voltages, UARTs need to support these new voltages as well. As a result, a new generation of UARTs has been developed to operate at 3.3V, 2.5V and 1.8V supplies. To reduce the power consumption further, new standalone UARTs offer powerdown mode features. These features allow the UART to reduce its power consumption to the microamp range while idling.
Along with lower power consumption requirements, a growing number of systems using standalone UARTs are looking into UARTs in the smallest possible form factors. Today the smallest form factor on the market is provided by NXP in the form of a 3.5 mm x 3.5 mm TFBGA package.
Low Resolution Clock Prescaler
A UART needs a clock source to generate a baud rate. The clock source can be created by an on-chip oscillator that requires an external crystal, or by an external oscillator. To ensure the baud rate is programmable while using a fixed frequency clock source, most standard UARTs use an integer divider, allowing the UART to divide the clock source by N ‹\[1, 2, 3...\]. The limitation of the integer divider is that lower integer values (i.e.1 to 10) offer a fairly course baud rate range. Some advanced high-speed UARTs, such as the NXP SC16C850L, are using a rational divider that allows the UART to divide the clock source by fractional numbers, enabling a much wider range of baud rates. The baud rate is then calculated according to the following formula: BR=F/(N + m/16). Where N is an integer ‹\[1 to 65K\] and m is an integer ‹\[1 to 16\]. The benefit of using a "rational divider" is that with a wider range of baud rates to program, higher performance and improved transmission accuracy are possible.
When two computing systems are communicating at very high data rates over long distances, a single ended method is not sufficient. Thus, RS485 with its differential signals are used to reduce noise on the network. RS485 is suitable for a multi-point communications network. However, for most integrated UARTs, designers need to write complex software to support RS485 features.
A growing number of new generation standalone UARTs are designed with RS485 features to reduce the complexity of the software running on the processor. These UARTs have a built-in feature that can detect the RS485 address automatically without intervention from the processor. This capability significantly reduces the CPU processing time because it eliminates continuous interruptions from the UART to the CPU. For standalone UARTs supporting the auto RS485 address detection, the host processor can enable the UART to detect its own address automatically and to inform the processor once the address is detected. In addition, the RS485 line driver direction can also be controlled automatically via an RTS (Request To Send) output pin, a 9-bit mode (aka multi-drop mode) to automatically-detect up to 32 (2-wire bus) and 64 (4-wire bus) slave device addresses.
Recent developments in processors and chipsets have driven the need to upgrade the performance of peripherals that frequently interface with them. The most popular and most common peripheral is the UART. Today developments in this space have shown that the standalone UART has evolved into a higher performance solution and, when designed into a system, can significantly contribute to offloading processing from the CPU and connectivity chipsets. The recent trends in standalone UARTs provide designers with a high-speed, low-power interface positioned to efficiently support connectivity solutions such as Bluetooth EDR. The broader feature sets of this new generation of UARTs provide designers with a value-add solution that contributes to further optimization of system performance and greater flexibility while reducing time-to-market.
Dr. Sylvie Kadivar is an international product marketing manager who can be reached at [email protected]. Handoko Chendra is an applications engineer; Robert de Gruijl is a senior design engineer; and Dong Nguyen is a senior application engineer. All are at NXP Semiconductors, Business Line Standard ICs.
Company: NXP SEMICONDUCTORS
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