Electronic Design

Framer/Concentrator Streamlines Sonet Line-Card Design

Though the financial health of telecom carriers is on the mend, their budgetary charts reveal continued cost-conscious operations. They'd rather not replace whole racks or modules to cope with the ever-growing capacity needs for internetworking. But by replacing line cards with new ones that feature higher speeds and other desirable features, carriers can quickly upgrade a system for minimal cost.

The latest chip from Exar Corp. may help these beleaguered companies. The XRT94L55 Cobra, a flexible Sonet framer/concentrator, greatly simplifies and facilitates the design of new line cards for Sonet/SDH equipment like add/drop multiplexers (ADMs), digital cross-connect systems (DCSs), and metro aggregation platforms.

The Cobra aggregates 16 total PECL inputs, divided into 12 OC-3/STM-1 (155.52 Mbits/s) and four OC-12/STM-12 (622.08 Mbits/s) lines, into an OC-48/STM-16 (2.4888 Gbits/s) line (see the figure). The lines on the right may come directly from optical transceivers or a backplane. The Cobra's internal transceivers include clock-and-data-recovery (CDR) circuits, eschewing additional circuits. The 4-bit low-voltage differential-signaling input and output lines on the left speed along at 2.488 Gbits/s. These lines can match up to Exar's XRT91L81 OC-48 transceiver chip. From that transceiver, the data goes to the optical transceivers.

A popular input option for the XRT94L55 is DS3 (44-Mbit/s time-division multiplexing) aggregation. This can be easily handled by the XRT94L43 DS3 concentrator chip, which can map 12 DS3 channels into a single OC-3 line.

The Cobra's 96-by-48 STS-1 internal cross-connect switches handle the aggregation. With its overhead transparency feature, the device can be configured so Sonet/SDH overhead bytes are transparently sent from low-speed to high-speed ports. Designers also can build systems that provide enhanced provisioning, grooming, and performance-monitoring capabilities.

Double-data-rate (DDR) port access capability exists on all of the Cobra's interface ports. It can process clock rates at half the clock speed of typical operation, which facilitates system design when interfacing the device with other ASICs or FPGAs. This decreases design timing overhead by enabling the clock to trigger on both the leading and trailing edges.

While some companies offer complete add/drop multiplexers (ADMs) on a chip, the Cobra and related support chips provide considerably more flexibility in configuring a design for a specific application. The XRT94L55 Cobra comes in a 780-pin ball-grid-array package. It operates at 3.3 V with 5-V-tolerant I/O lines. Samples are available now. Cost is $295 in 1000-unit lots.

Exar Corp.
www.exar.com

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