Implementing the On-the-Go supplement to the USB 2.0 specification, the USB OTG core features a USB port that can serve as either a master or a slave when connected to another USB device. The core includes special hardware to handle the host negotiation protocol, session request protocol, and other time-critical functions. It can be licensed for use in ASICs and FPGAs. FIFO interfaces are included, and up to 16 IN and OUT endpoints can be programmed in the core to further optimize it to a specific application. Supporting the core is a complete test environment that includes a behavioral model of the PHY software layer to allow for easy transaction simulation. The core's pricing varies by configuration and license type.
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