There appears to be no end to the functionality that can be added to the next-generation mobile phone. This trend is partially driven by network operators. After all, they can realize a higher annual revenue per user by offering handsets with greater functionality. Support for new applications also is critical. End users are eager to try applications like hot-spot Internet access, WLAN for the enterprise, and GNSS (GPS and Galileo) for new "find-a-friend" and E-911 services. Aside from the operator requirements, legislation is affecting this integration trend. Because it is limiting the use of cellular phones in automobiles, Bluetooth will most likely be added for hands-free headsets. Simultaneously, terminal manufacturers are looking to increase market share through the higher feature integration of games, entertainment radio (FM), television (DVB-H), longer battery life, and smaller size.
To support these emerging applications, engineers need to effectively integrate an increasing number of radios and peripheral functionality. New IC design approaches are therefore required. As to how these functions are integrated into cellular phones, the jury is still out. The question that designers need to answer is, "What provides the smallest, most power-efficient and effective solution while still hitting time-to-market objectives?" It's questionable if this goal is best achieved using a single-chip approach to design. In many cases, system-in-package or multichip modules may offer significant advantages.
Single-chip Bluetooth and IEEE 802.11 WLAN radio transceivers have demonstrated the technical and practical feasibility of integrating radio-frequency (RF) and digital circuits onto a single CMOS die. Complete GSM radios, which exclude the power amplifiers, have been developed using CMOS processes. They could conceivably be integrated with the digital circuits into a single-chip transceiver. Yet the decision of whether to integrate the two onto the same die is not as straightforward as it seems.
The designer's choices include flip-chip, system-in-package (SiP), and multichip modules (MCMs). Each option offers a proven approach with reliable assembly techniques—especially for designs that incorporate RF circuitry. Consider the following factors when determining the degree of integration for next-generation cellular chip sets:
- The time-to-market considerations that are associated with the risks of analog and digital integration
- The impact of the operating voltage
- The pure silicon economics of having a single, larger die as opposed to two or more chips with smaller die that use different technologies
Analog, RF, mixed-signal, and digital circuits are shrinking at different rates. Digital circuits, such as logic and memory, broadly follow Moore's law. As the circuits shrink with the square of the feature size, the overall cost per function also decreases. In contrast, the size of RF and mixed-signal blocks is typically determined by on-chip passive components like resistors, capacitors, and inductors. These components don't shrink. As a result, the cost per function of analog and mixed-signal RF circuitry rises when implemented on the state-of-the-art digital processes that feature smaller geometry (FIG. 1).
The most cost-effective approach to designing large circuits may be to use different dedicated process technologies that are optimized for the analog, RF, and digital functions. The number of additional mask steps, which are required to support analog functions, increases the relative cost of the digital functions. It therefore drives up associated costs in yield and test time. Keep in mind that processing ever-finer line widths demands equipment of increasing precision. As a result, the cost of exposure systems also rises. Systems that cost tens of thousands of dollars in the 1960s are now in the tens-of-millions-of-dollars bracket. Inevitably, this cost impacts market opportunities.
The supply voltage's influence also must be taken into account. As digital transistors get smaller and thinner, core supply voltages must decrease in order to avoid breakdown effects. They also must keep power consumption under control. Submicron processes that operate at core voltages of around 5 V are now a dim memory. The transition to 0.5-µm and below reduced core voltages to 3.3 V. Meanwhile, 0.25-µm gates reduced core voltages to as low as 1.8 V.
As the latest digital processes transition to 90-nm or smaller line widths, core supply voltages of 1.0 V or lower can be realized. These lower-voltage devices make it increasingly difficult for designers to create functional analog and mixed-signal RF circuits—especially if they have to interface to the real world. To address this low-voltage issue for the I/O pads of digital chips, designers can add larger-geometry devices with thicker gate oxide (typically from the previous-generation technology). In some cases, this approach will allow mixed-signal circuits to be added. If the area is significant, however, a more cost-effective approach would be to implement these circuits in a larger-geometry process.
Lowering the supply voltage decreases the voltage range that is available to represent analog signals. Thus far, designers have only been able to accommodate analog circuitry during process shrinks by creating new circuit topologies. Such topologies maximize the analog range. It's difficult to envision how this method can be sustained through further scaling of the power supply—particularly for geometries below the 0.13-µm node. If the analog range cannot be increased, designers are left with no alternative but to improve signal-to-noise ratios. Smaller feature sizes will make the device operate faster and at lower voltages. But this improved operation will be at the expense of both current and power consumption.
Shrinking process geometries also make "first-time success" increasingly unlikely. According to September 2003 presentations to Synopsys User Groups, no less than 61% of new application-specific integrated circuits (ASICs) and ICs require at least one re-spin.* This time-to-market problem is getting worse with increasingly complex designs—especially those with analog and digital elements.
Ten years ago, the majority of silicon re-spins were due to simple problems like connectivity errors. Modern design tools have eliminated most of these basic errors. But today's problems are much more insidious than the ones faced in the past. It's estimated that as much as 80% of the problems in a state-of-the-art design arise from a failure to account for some unanticipated physical effect. Such effects include artifacts that couldn't be modeled or anticipated before the design started.
Library models of digital circuits are more accurate than their analog counterparts, as the analog models always take longer to develop and properly characterize. In addition, designers must consider the interference from digital signals. In large deep-submicron chips, the noise from millions of fast-switching digital gates can pose serious problems. That noise will affect the performance of the adjacent mixed-signal and analog circuitry. Many products cannot tolerate a loss in performance due to noise generated by the digital circuits coupling into the RF circuits. For cellular standards, this intolerance is important for the receiver circuits, where sensitivity can be degraded. In addition, it affects the transmitter noise specifications. Failure to meet these specifications will prohibit sales, as the end product cannot be type-certified.
Although issues like these are at the forefront of developments in design automation, they're far from being solved. Many challenges confront the design layout, simulation, and verification that incorporate substantial digital circuits with RF, analog, and mixed-signal functionality. As a result, few designs can be completed without trying out silicon first.
All of these factors pose significant risks to first-pass success. If first-time success isn't achieved, the cost of re-spinning the device is alarming. Modern deep-submicron and nanometer foundry processes can approach $1,000,000 in mask costs alone. These costs can easily make up more than half of the cost of the total wafer.
Of all of the economic challenges that have been mentioned, the most serious one is missing the market window. Unlike the situation a decade ago, there is no second chance today. Being second to market equates to no market. The consumer markets for WLAN systems and cellular handsets serve as cases in point. New designs have a 12-month peak sales cycle. Typically, volume is ramped up in August and ramped down in August of the following year. IC designs that aren't ready to be designed in for August's production window will be too late to catch peak sales in November and December. Missing this design window will force the new design to compete for "next year's" design slot. In other words, the product is highly likely to be obsolete. The company must therefore find an alternative solution or cut or reposition the current product.
When these issues are combined with the NRE costs and time-to-market penalty that are incurred when re-spinning and re-testing the IC, they make the separation of RF/analog and digital circuits more appealing. In typical wireless designs, the digital elements are most frequently revised to take advantage of new market opportunities that have been spawned by user applications. Examples include the personal organizer or game software. Advanced functions and features that were previously only found on high-end handsets are now mandatory at the lower end of the market. To keep costs down, it may be sensible to integrate some of the functions that were handled by application processor ICs into baseband processors. But this approach increases complexity and time to market, as non-real-time functions and operating systems have to be combined with core, real-time, call-processing software.
In this application space, technical advances in analog circuitry are slow. In addition, developments take longer to merge in the market. Changes in radio standards are—if anything—even slower to evolve. Evolutionary time-scales for developments like GSM, GPRS, and EDGE are positively glacial compared with the market's rapid acceptance of organizer features, Java games, and polyphonic ringtones.
An emerging trend in the development of high-performance products is the use of system-in-package modules. These modules allow multiple technologies to be used within the same package. Today's multichip modules and chip-scale packages allow SiGe BiCMOS and multiple-geometry CMOS dies to be integrated into a single package with a chip-sized form factor.
Once, the primary argument for integration into one die would've been the offering of a smaller-footprint solution. Now that the stacking of die is becoming commonplace, this argument no longer works. The new approach allows memory and logic to be stacked into one package. That package is one-third the footprint of conventional designs. This technique can even be extended to include radio-frequency and mixed-signal circuits.
Multichip integration also offers additional areas of advancement, such as the flip-chip mounting of die. This type of mounting provides a smaller footprint by removing the bond wires at the periphery of the die along with the pads that are needed in the package. Flip-chip packaging also offers excellent ground connections by removing the bond-wire inductance. This latter point assists both the single-chip and the multichip RF and analog circuits. It improves the 'removal' of noise via the ground path. This aspect will undoubtedly ease the design of single-chip solutions by enabling grounding in the die's center with minimal inductance. As a result, high-performance power amplifiers can be integrated in silicon with the RF circuits. Both require similar process technologies for the optimum performance.
Arguments against flip-chip mounting do exist. One traditional argument pointed to the need for larger bond pads and pad pitches, which increased the die size. But modern flip processes can tolerate similar pad pitches. Or it's possible to use the same pad pitch by adding a re-distribution layer at post processing. In summary, flip-chip mounting offers a path to integrating multiple die in a space that's comparable to the area of single-die solutions.
CHIP-SET EVOLUTIONTypically, the life cycle of wireless chip sets progresses through four stages of evolution: early stage, maturing, commodity, and system-on-a-chip (SoC) integration (FIG. 2). During the early stage of development—before a standard fully matures—two-chip solutions generally provide the lowest-risk route to market. These solutions usually include a radio transceiver and a baseband IC, which incorporates the digital and mixed-signal logic, memory, and processing functionality. In many cases, the RF chip is derived from an existing product that operates in a similar frequency band. For example, many of the early Bluetooth radio chip sets were based on existing DECT architectures that were modified to operate at 2.4 GHz.
In early cellular-phone designs, multiple ASICs and standard components were combined into chip sets that supported the desired functionality with acceptable cost, size, weight, and talk time. The solutions were generally based on at least two digital chips: a processor and a DSP or ASIC. They also housed external SRAM and Flash memory, a low-integration radio, and audio and battery-management circuits (FIG. 3).
Through standard maturation and commoditization, cost and form factor drove the development of more integrated chip sets. Digital functionality—including the processor, DSP, and ASIC—was integrated into application-specific standard products (ASSPs). The large ASSP sometimes pushed the boundaries of cost-effective system integration. To complete the baseband processing, it was coupled with external SRAM and Flash memory. Due to the large amount of memory required for cellular-telephone systems, the primary memory blocks weren't integrated with the logic. The large memory would result in significant penalties associated with cost, flexibility, and yield.
To further increase the value, however, mixed-signal circuitry was integrated. Such circuitry included analog-to-digital and digital-to-analog converters for the audio and radio signal paths (FIG. 4). At this stage, these mixed-signal functions represented about 5% to 10% of the ASSP die area. Integration therefore made economic sense even though the circuits themselves were slightly larger when implemented in the digital process.
Now that the GSM standard has stabilized, chip sets are entering the final stage of development. But the economics of integration are less clear in future phases of the mobile phone's evolution. Consumers will demand additional wireless services like Bluetooth, WLAN, and GPS capability. In addition, the air interfaces will move from circuit-switched voice operation to packet-switched, "always-on" data connectivity. As these changes occur, cellular handsets will require up to a 10X increase in processing power, logic, and memory.
Thanks to Moore's law, the proportion of the die that's occupied by the digital logic will continue to decrease in proportion to shrinking geometry (FIG. 5). Several IC manufacturers have therefore decided to separate the analog and digital functions into two chips. They allow each half to be made in a cost-optimized process. Adding WLAN, Bluetooth, and GPS capability is initially achieved by integrating separate subsystems—each with their own RF, baseband logic, central processing unit (CPU), and memory—in a so-called "Velcro" approach (FIG. 6).
Some market leaders like Qualcomm are even going one step further. They're integrating all of the digital baseband functions of the peripheral technologies into the cellular-phone processor. The peripheral-radio ICs are implemented as separate, cost-optimized chips or modules. They're fabricated using low-cost RF processes like CMOS and SiGe BiCMOS, which can directly interface to the cellular baseband via a digital interface (FIG. 7). Here, the technical input to the choice of technology will be driven by two primary factors: the ability to integrate a high-efficiency power amplifier with the radio circuits and where the ADCs and modulator circuits for W-CDMA reside.
In contrast, other manufacturers are using a multichip-module platform approach as a stepping stone toward fully integrated SoC solutions. These manufacturers include Intel, Texas Instruments, and Renesas. Whether it comprises system-in-chip or multichip modules, the platform-module approach represents perhaps the most powerful of all integration strategies. The large, digital system-on-a-chip contains all of the digital functions. It can be easily and quickly ported to smaller geometries at low risk. At the same time, the analog, mixed-signal, and RF functions can be manufactured in low-cost, dedicated analog/RF processes. These processes provide the lowest cost point for the individual performance requirements. In turn, the devices can be individually cost-optimized as new processes emerge and are properly characterized. From a chip-vendor perspective, there will most likely be a better return on adding the next-generation signal-processing features, such as video coding and decoding, than there would be for adding some analog or radio circuits.
By using this plug-and-play modular approach to product design, product manufacturers can maintain the cost advantage of using a common core platform. At the same time, the manufacturers have the flexibility to choose which wireless standards to support. They also can select the optimal RF chip set or module for each function.
The trend of adding analog and mixed-signal functions to CMOS digital chips has been extended to the integration of complete radios. As long as they offer the lowest-cost solution and their timing hits the market window, these single-chip radios will be successful in products that support single or multiple wireless protocols.
For high-volume products that require significant digital signal processing, large CMOS system-on-a-chip solutions will continue to absorb the digital circuits of the peripheral functions. It is believed that the functionality's evolution rate won't provide enough time to integrate radio and mixed-signal circuits. Outside of the static markets, the radio circuits will go the way of the analog and mixed-signal functions in the cell phone: They'll be implemented in an appropriate technology in a separate IC or module.
For high-volume wireless products, the main reason for not heading to single-die solutions is time to market. Time to market must be guaranteed in order to ensure a return on investment. Right now, it makes sound business sense to use the latest CMOS technology to shrink the digital circuits and memory in a timely fashion. Keep the analog, RF, and mixed-signal functions in an appropriate technology and just use system-on-a-chip packaging.
*Source, ESNUG/Aart de Geus, Chairman and CEO of Synopsys, as reported by Peter Clarke in Silicon Strategies, 09/10/2003, 9:14 AM ET.