Electronic Design

Key Design Aspects Of CMOS Image Sensors Revealed

What’s going on inside the latest cameras has a lot to say about the state of the art in digital imagers. This report offers tear-down analyses of CMOS image sensors (CISs) in mobile phones and professional digital single lens reflex cameras manufactured by Canon, Micron, Omnivision, Sony, and Toshiba.

It’s particularly interesting to examine the cell-phone end of the spectrum. CMOS image sensors have become the image capture technology of choice for the cost-sensitive, high-volume application of mobile phones. Today, Nokia and Motorola sell more digital cameras annually than traditional digital camera manufacturers. Today’s camera phones can offer optical resolution from 1 to 3.2 Mpixels.

CMOS has all but totally eclipsed CCD technology for mass-market image sensing. The world’s leading IDMs and fabless firms have invested in the development of CMOS image sensors to replace CCD image sensors. This investment has dramatically reduced CMOS image sensor cost and size and significantly boosted performance. Competition for the sockets is fierce. Innovation happens as often as 10 to 12 times a year, with competitors leap-frogging each other’s new products to get the all-important design wins in upcoming handsets.

This article details a few of the important aspects of CIS design: process-independent linear voltage gain; the extension of dynamic range by double integration; and lowering current consumption in chopper–type comparators.

Process-independent linear voltage gain
Canon’s 704F 6-Mpixel CMOS image sensor illustrates an approach to process-independent linear voltage gain. The IC is built on a process with three metal layers and one poly layer. It incorporates the sensor array and the analog front end (AFE) in one die (the sample analyzed by Chipworks was taken from a Canon EOS DS6041 digital still camera).

Figure 1, which is a simplified schematic of the AFE in the 704F, illustrates the basic idea of the front end. Typically, a fixed transconductor is a differential amplifier linearized through resistor (RE) degeneration. In a bipolar differential amplifier, if the VBE voltages of the differential transistors are constant, then the differential input voltage Vi appears across the degenerative resistor (RE). Thus, the emitter currents flowing through the emitters of the differential pair are:
IE1 = IS + VI /RE
and IE2 = IS – VI /RE

where IS is the differential bias current.

Assuming that the degenerative resistor is much bigger than the emitter resistance (that is, that RE >> re), the differential output current is:

iO= VI /(2re + RE)

Because Gm = io/vi, the transconductance of the differential circuit is simply a fixed value of 1/RE:

Gm = 1/(2re + RE)

where re <<RE.

Recall that re depends on the transistor emitter current IE, and that IE can’t be too small if re is to be negligible in comparison with RE. If this requirement isn’t met, the varying VBE voltage will result in the output current being a significant nonlinear function of the input voltage.

To solve the problem, single-stage amplifiers can be added on the input of the differential pair to bypass the effects of the V\\[subscript\\]BE\\[/sub\\] voltage and force the emitter voltages to be equal to those of the differential input voltage V\\[subscript\\]I\\[/sub\\]. This assures that:

GM = iO/VI = 1/RE

In its CIS 704F, 704W, and 706P series of CIS ICs, Canon combines two linear fixed-transconductors to perform correlated double-sampling (CDS) in the AFE. The first fixed transconductor, shown on the left side of the schematic in Figure 1, in the blue highlighted area, consists of the differential pair (224 and 225), programmable degenerative resistor RE1, current bias (232 and 235) and active load (236 – 239).

There are two single-stage amplifiers connected to the inputs of the fixed transconductor. One such amplifier (highlighted in pink) consists of the differential pair (214 and 215), current bias (216) and active load (221, 226, 217, 218). The first fixed transconductor calculates the difference between the actual photo signal and the reset signal represented by the differential input voltage, VINP– VINN. The differential output current is then i1 = 2(VINP– VINN)/RE1.

The second fixed transconductor (yellow highlight), is identical to the first one except that the degenerative resistor is a constant value RE2. The second fixed transconductor calculates the difference between the resulting output voltage VOUT and a voltage reference VREF. Thus,

i2 = 2(VOUT - VREF)/RE2

Since the two fixed transconductors have high output impedance, their output currents are made equal and opposite. Thus, i1 = -i2, and therefore:

VOUT = (VINN– VINP)*RE2/RE1 + VREF

Both RE1 and RE2, which are of the same resistor type (Si-poly), are laid out the same. As a result, they track with process variations and VOUT won’t be affected.

Extending dynamic range by double integration
One of the prominent problems in CIS and charge-coupled device (CCD) design is dynamic range. Some scenes imaged with electronic cameras can have a wide range of illuminations, with intensities varying by over 100 dB or more. The dynamic range determines the ratio of illumination between the brightest area and the darkest area an image can have for an image sensor to detect and process it without saturating. The human eye has a dynamic range of about 90 dB and camera film of about 80 dB, but a typical CCD or CIS has a dynamic range of only 65 to75 dB.

The intrascene dynamic-range (DR) capability of a sensor is measured as:

DR = 20 log(S/N)

where S is the saturation level and N is the root-mean-square (rms) read-noise floor measured in volts.

One of the most common techniques in improving the dynamic range of a CIS is multiple sampling during integration time. The AFE in the Micron MT9D011 CIS device uses an unusual circuit configuration to accomplish this. Two samples of the photo signal are taken during the integration period. Then these two samples are amplified with two different gains and are summed. (This technique is also used in other Micron CIS devices, such as the MT9V43 and MT9T012.)

The MT9D011 IC is a three-metal, two-poly-layer CIS, built using 0.18-micron technology (Figs. 2a and 2b). It uses two switched-capacitor, gain-amplifier stages connected in series. Both of the op amps used in each stage (not shown) are folded-cascode, differential amplifiers with common-mode feedback circuitry. Each op amp has a pair of pins for the differential input voltage, another pair for the differential output voltage, and IR2, VR2, and ENABLE pins for bias and control signals.

In Figure 2a, the second-stage gain amplifier is shown in detail. A set of nodes designated PGA1OUT (highlighted in pink) accepts signals from the first stage and another set, designated PGAOUT (green), passes the signal on to the ADC circuitry. Feedback capacitors 367 and 379 (blue) are connected to the differential inputs and outputs of the op amp through the switches 370 and 382 (yellow). The capacitors are of the metal-insulator-metal type.

Recall that, in theory, double integration is achieved by reading two signals from the pixel array during the integration period and processing them at different gain values. Then, the two resulting amplified photo signals are summed before being passed to the ADC circuit. In this IC, those gain values are set by the variable capacitor circuits (highlighted in orange) and the two feedback capacitors (highlighted in blue).

That is, the ratio Cvar1/C367or379 sets the gain applied to the first photo signal, and


(Cvar1 + Cvar2)/C367or379 sets the gain applied to the second photo signal.

The values of Cvar1 and Cvar2 are selected, as in Figure 2b. Essentially, seven capacitors, stepped in size by a factor of 2n, are connected to the bus designated PRG2\\[6:0\\] in Figure 2a.

Lowering current consumption on chopper-type comparators
In recent years, chopper-type comparators have become common in the ADC AFE, especially for high-resolution CISs that also require high speed and low power consumption. The basic structure of a chopper-type comparator consists of a multiplexer, an autozeroing-two-stage inverter/amplifier, and coupling capacitors (Fig. 3a).

The multiplexer switches the input to the first node of the first coupling capacitor (C1) between a reference voltage VREF and the photo signal VIN. A second coupling capacitor (C2) transfers the data from the first inverter/amplifier stage to the next. Autozeroing, or self-offset cancellation function, is achieved by closing both transfer gates (TG1 and TG2). This forces the inverter/amplifier inputs to the same voltage as their outputs.

Only one clock, CLK, and its complement, CLK~, are needed to control the operation of this type of comparator. When CLK is HIGH, VREF is applied on the first node of the first coupling capacitor. At the same time, TG1 and TG2 are closed for autozeroing. When the CLK signal goes LOW, VIN– V\\[REF is applied to the first node of the first coupling capacitor and is amplified by the inverter/amplifier stages.

In a typical design, the inverter/amplifiers are implemented as multiple stages. The first stage amplifier has shorter gate length—mainly for high-speed operation, along with low gain, to minimize any channel-length-modulation effect. The second-stage amplifier has a longer gate for higher gain, but slower operation. Also, to avoid undesired clock feedthrough common in transfer gates, the gate widths of the p- and n-channel transistors of TG1 and TG2 are designed to have the same gate-drain and gate-source capacitances.

One of the main drawbacks of this type of circuit is its current consumption. During the autozeroing phase, when the inputs of the inverter/amplifiers are forced equal to their corresponding outputs, the currents flowing through the amplifiers are at their maximum. The common solution for such a problem is to reduce the width-to-length ratio of the amplifiers. Unfortunately, this solution affects the comparator’s gain and speed.

The Sony IMX011 is a 2.1-Mpixel CIS with three metal layers and one poly layer built using 0.18-micron CMOS technology. It is distinguished by using an improved chopper-type comparator (Fig. 3b).

The circuit structure and operation is almost like that of Figure 3a, except for the addition of the voltage-controlled current sources connected to the sources of the p-channel transistors in each stage. The current flowing through the inverter/amplifiers are then controlled through the input node V\\[subscript\\]BCC\\[/sub\\] at the top of the schematic.

By varying the voltage potential on VBCC, the current flowing through the inverter/amplifiers can be reduced almost to zero in standby mode, allowed to remain at maximum during the auto-zeroing phase, or set at an optimal value during amplification or sampling. On the input side, transfer gate 369 and switchable MOS capacitors provide clock feedthrough compensation.

In the Samsung S5K3AAEA03 and S5K3BAFB CMOS image sensors , a similar approach is used (Fig. 3c). The first IC is a 1.3-Mpixel CIS with four metal layers and one poly layer that’s built on 0.18-micron CMOS technology; the second is a 2-Mpixel CIS with four copper metal layers and one poly layer that’s built on 0.13-micron CMOS technology.

In this example, both of the inverter/amplifier stages consist of two cascode p-channel transistors and two cascode n-channel transistors. Further, the first stage is connected to an n-channel voltage-controlled switch, while the second stage is connected to a p-channel voltage-controlled switch.

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