Electronic Design

Non-PLL Clock Boosts Stability And Jitter At High Frequencies

Every communications product and system needs a highly stable and reliable clock. Stability and reliability both are harder to achieve at higher clock frequencies--especially over 100 MHz.

While lower-frequency crystals with good stability often are used with a phase-locked loop (PLL) multiplier to get the desired higher frequency, the PLL often increases the jitter problem. On top of that, crystals that operate above 100 MHz are inherently thin and tend to be less reliable than thicker crystals at the lower frequencies. They aren't as stable, either.

Operating from 100 to 160 MHz, the S1614XP and S1613XP low-voltage CMOS oscillators from Pericom Semiconductor solve this problem by combining a Pericom IC with a SaRonix quartz crystal design. Pericom uses a thicker quartz blank paired with a non-PLL, patent-pending IC design for a stability of ±25 ppm over the commercial temperature range and ±50 ppm over the industrial temperature range. The computed clock jitter is only 0.5 ps 1-sigma rms.

These oscillators are designed especially for critical server, networking, and storage applications. Standard available frequencies include 100, 106.25, 125, 133, 150, 155.52, and 156.25 MHz. Other frequencies are available on special order. The units are housed in a 5- by 7-mm hermetically sealed ceramic package. They operate from 2.5 or 3.3 V and draw less than 30 µA.

Ordering times range from stock to eight weeks. Prices start at $1.25 for 10,000-unit quantities.

See associated figure

Pericom Semiconductor Inc.
www.pericom.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish