One-Chip NPU Halves Cost

April 14, 2003
The PayloadPlus APP540 network processing unit (NPU) integrates four separate chips into one seriously powerful next-generation network processor. The integrated chip cuts product development costs by at least 50% compared with the nearest...

The PayloadPlus APP540 network processing unit (NPU) integrates four separate chips into one seriously powerful next-generation network processor. The integrated chip cuts product development costs by at least 50% compared with the nearest competitors. Developer Agere Systems says the processor could potentially improve service revenue capabilities as well as the reliability of network equipment over the next few years. It's also a good fit with OC-48 systems.

The APP540 comprises a programmable traffic manager, a multifield classifier search engine, a network processor, and an Ethernet media access controller (MAC) (see the figure). As one chip, it can process data at speeds up to 5 Gbits/s. The classifier determines what to do with the voice, video, or data entering the equipment.

The classifier uses 2.6 Mbytes of on-chip SRAM or additional external SRAM if needed instead of the costlier content addressable memory (CAM) most competitors use. The network processor carries out the forwarding directions the classifier gives it while the traffic manager helps optimize the bandwidth of the data exiting the network processor. The APP540 provides 16 10/100-Mbit/s and four 1-Gbit/s Ethernet MAC interfaces, the most widely used local-area network standard.

Competitive solutions require two to four chips to accomplish the same functions. The single-chip approach cuts cost, size, and power consumption while improving reliability. The processor targets enterprise office building and telecom central-office equipment like multiservice provisioning platforms and switches, routers, data center switches, 2.5G and 3G wireless systems, and Ethernet over Sonet add/drop multiplexers.

The APP540 supports the POS-PHY level 3 (two of them), GMII, SMII, and PCI interfaces. The Agere Festino platform supports software and applications development. The Functional Programming Language (FPL) and the patented Pattern Processing Engine (PPE) significantly reduce programming time and cut code size by a factor of 25 or more over C or other NPU languages.

Samples of the APP540 will be available this month with 10,000-unit pricing at $295. A smaller version, the APP520, has two 1-Gbit/s Ethernet MACs and costs $195 in the same quantities.

Agere Systems
www.agere.com/micro/his

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