Electronic Design

Physical-Layer Interfaces Reach Beyond 10 Gbits/s

Sonet and Ethernet PHYs emerge as the core technologies for WANs, MANs, and LANs.

In the popular movie Top Gun, actor Tom Cruise says, "I feel the need, the need for speed!" If you share his desire to go mach 2 with your hair on fire, then hot new Sonet (synchronous optical network) and Ethernet physical-layer interfaces (PHYs) are for you. With new standards having defined higher data rates for these key networking technologies, both are increasingly being adopted at all levels as the Internet and broadband access continue to grow.

Sonet, a one-clock, synchronous PHY for high-speed data transfer over fiber-optic cable, has long been the workhorse for long-distance voice and high-speed data. With steadily growing speed, it readily carries other data formats like ATM, as well as Ethernet and IP packets. Many carriers have already rolled out OC-48 (2.488-Gbit/s) systems, and most will soon implement OC-192 systems at 9.952 Gbits/s (generally called 10 Gbits/s, or 10GE). There's wide agreement that in the near future, OC-768 systems running at 39.8 Gbits/s (usually called 40 Gbits/s) will be commonplace. These speeds, combined with dense wavelength-division multiplexing (DWDM), promise terabit and petabit data rates.

Ethernet currently has several 100-Mbit/s variants, and users are rapidly adopting 1-Gbit/s (IEEE-802.3z) systems. Also on the way are 10-Gbit/s (IEEE-802.3ae) systems. Although this standard is not yet ratified, several semiconductor manufacturers have already announced parts supporting the 10-Gbit/s Ethernet standard. So no longer is Ethernet just a LAN. Using an optical PHY, it's now a viable metropolitan-area (MAN) and even a wide-area network (WAN) alternative.

Ethernet will continue to be used in larger LANs. It will let enterprise LANs scale to even higher rates with minimal expense and reconfiguration. Many enterprises are just now moving to 1-Gbit/s Ethernet, but those systems can be aggregated into 10GE systems, allowing the enterprise to leverage the hundreds of millions of Ethernet ports in the world.

With 10-Gbit/s bandwidths at our disposal, MANs and WANs suddenly become possibilities. For example, 10GE could be used to implement low-cost MANs using existing dark fiber for a lower cost than a T3 or OC-3 (155.52-Mbit/s) line. Potentially, significant cost cuts could result from employing 10GE in new MAN mesh-switching arrangements and/or reducing the need for expensive routers and switches at point of presence (POP) connections.

With WANs and the core of the Internet currently at 10 Gbits/s, or moving there, 10GE becomes a WAN option too. At 10 Gbits/s, compatible Sonet OC-192 systems converge with 10GE systems. Although Sonet can additionally carry packet data, like ATM and IP, as well as Ethernet data, it does so for a price. Without the need for complex framing, concatenation, and protocol conversion, 10GE will make extending the LAN and the MAN to the WAN much easier. No doubt, 10GE will be a favorite among MAN carriers and ISPs looking to simplify their connections to the WAN, or even to implement their own WANs up to about 100 m. 10GE unifies LANs, MANs, and WANs.

At 10 Gbits/s, Ethernet will be simpler and cheaper than any equivalent OC-192 Sonet system. But it's not likely to put Sonet and ATM out of business. Sonet's installed base is just too big to ignore. It will continue to grow because of its extreme reliability and contribution to quality of service (QoS). But 10GE systems will eventually coexist and work together with the legacy Sonet infrastructure.

Last but not least, 10-Gbit/s hardware is making its appearance in short-distance interconnections between equipment and in buses and backplanes. Parallel data transfers have gone about as far as possible, literally and figuratively. Most new backplanes use high-speed serial links to carry data from chip to chip or box to box. The newer, faster PHY chips are ideal for these applications.

Layer 1 of the International Standards Organization's Open Systems Interconnections (OSI) reference model, the PHY, includes the transmission medium—typically twisted pairs or fiber, the connectors and mechanical interfaces, and definitions for bit voltage levels and speeds. This layer additionally defines electrical interfaces to the medium, synchronization, clock and data recovery, data-stream format, serial-to-parallel and parallel-to-serial conversion, and line encoding.

Many of these functions are being combined onto a single chip. Now, layer 1 PHY chips even include functions that are normally part of layer 2, like framing and error correction and detection.

The Sonet PHY is composed of multiplexers that take in slower-speed bit streams and aggregate them into a single higher-speed signal for transmission. Aside from the laser transmitter, the PIN or avalanche photodiode, and a transimpedance amplifier (TIA) in the receiver, the PHY consists of multiplexers and demultiplexers, clock and data-recovery (CDR) circuits, and FIFO buffers. Typical laser wavelengths are 850 nm for short-reach systems, 1310 nm for longer reaches, and 1550 nm for the long haul.

Increasingly, Sonet systems are using the multiwavelength DWDM transmissions, with as many as 40 or 80 different channels per fiber. The use of splitters and advances in filters and other optical components make possible 160 and more wavelengths per fiber.

Regarding the IEEE-802.3 Ethernet standard, it defines several different PHYs, such as RG-8/U (10Base-5) and RG-58/U (10Base-2) coax cable and twisted-pair (10Base-T) wiring. It even includes an optical fiber interface (FOIRL), although it's rarely used. The fiber distributed data interface (FDDI) is deployed in backbone applications.

The earliest Ethernet systems mostly used coax cable, but twisted pairs dominate today. Virtually all Ethernet LANs use Category 5 (CAT5) twisted-pair wiring with RJ-45 connectors, including the original 10-Mbit/s systems, the newer Fast Ethernet systems at 100 Mbits/s, and even 1-Gbit/s Ethernets. Transmitting 1 Gbit/s on copper is tough, though, at least for any distance. It's much easier with fiber. For forthcoming 10-Gbit Ethernets, the primary PHY is fiber.

Gigabit Ethernet is a fully approved standard. Many manufacturers make chips, transponders, network-interface cards (NICs), hubs, switches, and other components for use in LANs. It's primarily used as a backbone for large LANs. But as costs come down, more and more Gigabit Ethernet is showing up on the desktop, and even in some smaller MANs. A new study group within the 802.3 standards body, called the Ethernet in the First Mile (EFM), is promoting 1 GE as an inexpensive way to implement fiber in the home.

Final ratification for 10GE Ethernet by the IEEE-802.3ae Task Force is expected by early 2002. Yet IC makers are already taking a chance on the almost-completed preliminary standard and producing some 10GE PHY ICs.

The 10GE standard subdivides the PHY into a physical media dependent (PMD) layer and a physical coding sublayer (PCS). The PMD is the optical transceiver, while the PCS consists of the 8B/10B coding, serializer/deserializer (SERDES), and multiplexing functions. The 802.3ae standard defines two PHYs, a LAN PHY and a WAN PHY. The WAN version simply extends the transmission distances with a different PMD. Some proposed 10GE PHYs will have the following laser wavelengths, types of fiber, and minimum operating distances:

  • 850 nm, multimode, 65 m
  • 1310 nm, WWDM, multimode, 300 m
  • 1310 nm, WWDM, single-mode, 10 km
  • 1310 nm, serial, single-mode, 10 km
  • 1550 nm, serial, single-mode, 40 km

The WWDM above refers to wide wavelength-division multiplexing, which calls for several wavelengths of light to carry simultaneous bit streams in the single fiber.

PHY chips are found in several types of end equipment, as well as in bus and backplane designs. But most end up in optical modules, or transponders, that contain the laser and the photodiode, and inline cards or NICs. Chips em-bodying the PHY's physical circuitry go by the generic term transceivers, or SERDES chips.

Semiconductor manufacturers have made it easier to implement the PHY. The newest transceiver ICs now put practically everything necessary on one chip. Some chips have the flexibility to be used in either Sonet or Ethernet systems with the proper configuration.

Applied Micro Circuits Corp. (AMCC) offers the S3097/98 multiplexer/demultiplexer chips for OC-192 Sonet/SDH equipment. These second-generation versions of the S3091/92 trans-mitter/receiver ICs have been shipping since 3Q last year. The S3097 transmitter gets its 16-bit input in an LVDS bus. The chip has the parallel-to-serial circuits, multiplexer, and clock-synthesis unit. Its output is sent to a separate laser driver.

The S3098 companion receiver includes a post amplifier for the PIN or APD and TIA, a CDR unit, demultiplexing, and serial-to-parallel conversion. Internal voltage-controlled oscillators (VCOs) in both units operate from 9.953 to 10.709 GHz to accommodate the data format and any forward error correction (FEC) or lack thereof.

These SiGe chips draw about 3.1 W of power and meet all OIF and ITU standards. The 16-bit LVDS bus conveniently interfaces to AMCC's framer chips.

AMCC also recently announced plans for OC-768 products, which include the TIA, laser driver/modulator, multiplexer/CSU and PA/CDR/demultiplexer, and framers in increasingly more-integrated form. The first available product is the S76800 TIA. This SiGe biCMOS IC handles data rates of up to 48 Gbits/s and provides either return-to-zero (RZ) or nonreturn-to-zero (NRZ) outputs to the receiver. Samples are available now, with production to take place this June.

A good example of today's fastest PHY chips is the recently announced Broadcom BCM8150 single-chip OC-192 Sonet/SDH transceiver. This chip is part of Broadcom's X-PHY product family, a line of chips for both Sonet and 10GE applications. The BCM8150 integrates the multiplexer, demulitiplexer, clock multiplication unit, and CDR circuits in 0.18-µm CMOS. It only consumes 1.3 W, which is exceptional for a chip of this speed and complexity.

Broadcom has a complete line of chips to complement the BCM8150 for Sonet or 10GE equipment. The BCM8120/21 is an OC-192 multiplexer/demultiplexer chip set with FEC. The BCM8130/31 is similar to the BCM-8120, but it also works with 10GE. The BCM8710/11 multiplexer/demultiplexer has an XSBI interface for 10GE applications, while the BCM8701 is a Sonet framer/mapper for OC-192.

The X-PHY line of chips is based on designs from NewPort Communications (acquired by Broadcom last October). NewPort was the first company to make an OC-192 transceiver in CMOS.

Conexant Systems also produces a speedy transceiver for Ethernet or Fibre Channel systems and chassis-to-chassis and backplane applications. Called the CX27204, it contains four 3.125-Gbit/s transceivers that include the usual features, such as SERDES, CDR/CSU, 8B/10B coding, FIFOs for buffering, and even on-chip termination resistors.

The IC's double-data-rate LVTTL parallel interface is 32 or 40 bits, depending on the use of 8B or 10B coding. The serial output is differential and can be deployed with 50- or 75-Ω pc boards, twisted pairs, coax, or fiber media. It draws less than 2 W with a 2.5-V supply.

Infineon Technologies' FOA6100, designed for both Sonet OC-192 and 10GE applications, can be employed in WAN and MAN equipment, including add/drop multiplexers and digital cross-connects. The SiGe FOA6100 consumes a low 1.5 W at 3.3 V.

This 10-Gbit/s transceiver performs both SERDES and multiplexing/demultiplexing functions. For serializer operations, the clock is derived from an on-chip clock multiplier with a PLL synthesizer and a 10-GHz VCO. The input reference clock is 622 MHz. In addition, the chip contains a CDR unit that works with a PLL and VCO to generate the 10-GHz clock for deserializer operations. The parallel inputs are LVDS-compatible, while the serial I/O uses current-mode logic (CML).

Other features are a byte-alignment and frame-detection unit, and circuits for line loop-back and diagnostic loop-back modes. Parity generation and checking circuits are included. The chip meets all ITU, Bellcore (Telecordia), and OIF standards. It comes in a 156-pin BGA package.

Agere Systems, formerly Lucent Technologies, also recently announced some chips for this market. The field-programmable system chips provide flexible line interfaces for 10GE networks. One is the ORLI10G line-interface chip, which incorporates the 10-Gbit MII (XGMII) and the 10-Gbit serial-bus interface (XSBI) to optical transponders. It contains 400 kgates of programmable logic for customer-specific applications.

A second chip, the ORT82G5, is a SERDES transceiver with eight 10-Gbit attachment-unit interface (XAUI) channels in standard-cell logic operating at up to 3.125 Gbits/s. (XAUI is a chip-to-chip interface used in backplane and bus designs.) The chip also includes 600 kgates of programmable logic for customer IP. Both the ORLI10G and ORT82G5 chips are OIF-compliant and made with Lucent's ORCA FPGA technology and 0.13-µm CMOS.

Another advanced PHY chip comes from PMC-Sierra. The PM8355 QuadPHY II contains four 2.0- to 3.125-Gbit/s transceivers for employment in 10GE, Fibre Channel, or Infiniband applications. It has a 9/10-bit parallel XGMII (10-Gbit MII) to/from the Ethernet MAC and differential LVDS or PECL-compatible serial-in/serial-out lines that comply with the 802.3ae 10-Gbit XAUI serial interface standard.

All of the Ethernet physical media attachment (PMA) and physical media dependent (PMD) PHY circuits are fully implemented on-chip. Features include 8B/10B line coding and decoding as called for by the standard, SERDES, clock synthesis and recovery, and FIFO buffers to assist in synchronizing incoming data to the local clock. This full-CMOS chip operates from 1.8 V with a 2.5-V-tolerant I/O, and it consumes less than 2 W total. The chip is housed in a 19- by 19-mm, 289-pin BGA package.

Another four-channel 3.125-Gbit/s transceiver chip is Texas Instruments' new TLK3104SA (Fig. 1). The transceivers can operate independently or synchronized for full 10-Gbit/s throughput. The chip supports the XGMII parallel interface and the XAUI serial output interface. All required circuits, like 8B/10B encoding/decoding, SERDES, and FIFO clock buffering, are on board. Moreover, the TLK3104SA has a built-in pseudorandom bit-stream (PRBS) generator and verification circuit to loop-test all circuits. It supports the JTAG test interface, too. The 0.25-µm CMOS chip operates from 2.5 V, consumes about 2 W, and comes in a 289-pin plastic ball-grid-array (PBGA) package.

Velio Communications has taken this kind of circuit one step further and packaged eight 2.5- to 3.125-Gbit/s transceivers in one chip. Called the VC1003, this four-channel 0.18-µm CMOS chip has all of the features associated with the aforementioned chips, yet only consumes 2.1 W maximum.

Vitesse Semiconductor has long been a producer of very high-speed data-communication ICs. Starting with GaAs, the company has now migrated to CMOS with one of the most complete 10-Gbit/s chip product lines available.

For example, the VSC7226-01 quad transceiver is a four-channel 3.125-Gbit/s IC. Designed for Ethernet or Fibre Channel, it also works well in serial backplanes. Like most of the other chips, it features 8B/10B coding, elastic FIFO buffers, and the usual CDR circuits. The parallel I/O is SSTL_2-compatible at up to 312.5 Mbits/s, while the serial I/O is XAUI-compliant with PECL features. Additionally, the chip has a JTAG test port and BIST circuits. It consumes 3 W at 2.5 V and comes in a 21-mm2 256-pin BGA package.

Another Vitesse chip for Sonet applications is the VSC7166. Designed for OC-192 applications, this 16-bit parallel-input SERDES has 12 output serial channels (see Electronic Design, "Serializer/Deserializer Creates Low-Cost, Short 10-Gbit/s Optical Links," Feb. 5, p. 41).

Vitesse recently introduced the VSC8184/8185 multiplexer/demultiplexer chips that run at 11.5 to 12.5 Gbits/s. Designed to support FEC, they integrate SERDES and CDR functions for OC-192 applications (Fig. 2). The multiplexer features a 16-bit OIF-compliant LVDS parallel interface that runs at 719 to 781 MHz. A 622-MHz data input clock is required to run the on-chip PLL-based clock, which meets ITU jitter standards. The 16-by-7 FIFO simplifies parallel input timing. The differential output is designed to drive a 50-Ω load.

In the VSC8184 demultiplexer, OC-192 serial data is demultiplexed into 16 channels of LVDS output plus parity (Fig. 3). The CDR circuit keeps the internal VCO locked to the input. Both chips come in a 90-pin thermally-enhanced ball grid array (TBGA) and together consume less than 3.5 W at 3.3 V.

Also, Vitesse offers the VSC8173/74 versions of these chips for non-FEC applications, such as optical modules. The VSC8175 multiplexer is available for RZ output requirements.

Making 10-Gbit/s parts is tough. It can be accomplished with GaAs, but most semiconductor companies can't access GaAs fabs. SiGe also works, but again, the number of available fabs is limited. Therefore, most companies in this market have decided that plain old silicon is best. With the newer 0.25-, 0.18-, and even 0.13-µm processes, 10 Gbits/s can be obtained in CMOS.

But in the quest for OC-768 speeds at 40 Gbits/s, CMOS may run out of steam. Some companies are already exploring a variety of group III-V semiconductor element combos, like AlInAs and InGaAs, as well as the more exotic InP. But who knows? Silicon has fooled us all more than once.

Companies That Contributed To This Article
Agere Systems (formerly
Lucent Technologies)

(908) 508-8412
www.lucent.com/micro

Applied Micro Circuits Corp.
(858) 535-4260
www.amcc.com

Broadcom Corp.
(949) 450-8700
www.broadcom.com

Conexant Systems Inc.
(408) 467-4496
www.conexant.com

Infineon Technologies
(650) 691-1488
www.infineon.com

PMC-Sierra Inc.
(604) 415-6000
www.pmc-sierra.com

Texas Instruments Inc.
(214) 480-7487
www.ti.com

Velio Communications Inc.
(408) 434-9280
www.velio.com

Vitesse Semiconductor Corp.
(805) 388-3700
www.vitesse.com


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