Wireless Systems Design

The Quest Continues For The SDR Holy Grail

Adaptive And Reconfigurable Technologies May Be The Best Solution For The Baseband Portion Of Software-Defined-Radio Systems.

The Holy Grail of software-defined radio (SDR) is flexible bandwidth combined with a flexible air-interface system. Such a combination could be tuned across a broad RF band that is capable of both time- and frequency-duplex operation. The technology that could enable this reality remains out of reach, however. This is particularly true when it comes to the needed RF components.

For SDR, one of the greatest challenges is the duplexing of transmit and receive signals. Time-duplex systems solve the transmit-to-receive interference problem by operating the receiver and the transmitter in different time slots. Only one of them is active at any instant in time. Simple switches can then be used to connect the receiver and transmitter to the antenna. Time-duplex systems are common in early TDMA systems, such as GSM and ANSI-136. In contrast, half-duplex systems are usually found in the public-service domain and wireless-LAN systems.

Most 3G wireless systems differ in that they require full-duplex operation. In this mode, both the transmitter and the receiver operate simultaneously on separate frequencies. The transmitter frequency must therefore be isolated from the receiver frequency. This task is handled by high-power filter structures, which are known as duplexers. But fully tunable duplexers are difficult to design and build. They suffer from higher insertion losses than their fixed-frequency cousins (e.g., a single-band cellular duplexer). Plus, they tend to be bulky and expensive.

The RF domain faces another obstacle in the development of radio-frequency power amplifiers. This sector demands power amplifiers that are capable of operating over broad bandwidths with a wide variety of power settings. They also should have high linear requirements. Although it is possible to build such power amplifiers, they are typically expensive and high in power consumption. These drawbacks become clear when they are compared to power amplifiers that are optimized for a specific air interface and designed to operate over narrower frequency bands.

Analog-to-digital converters (ADCs) form the last RF hurdle. ADCs must operate over the broad dynamic range. To cover the diverse air interfaces, they also need to function at high speeds. Consumer products within the wireless-/mobile-device category require integrated circuits (ICs) that are low in power consumption and cost, but high in performance. Currently, ADCs that meet such requirements—while being capable of SDR-type operation—are largely nonexistent.

Fortunately, today's world is much simpler than the software-defined-radio ideal. Governmental agencies designate frequency bands for specific uses. Standards bodies design wireless systems that are evolutionary within these allocations. As a result, the amount of flexibility that is needed from the RF interfaces is greatly narrowed.

Figure 1 illustrates a version of an SDR that applies to the commercial cellular market. In this design, frequency bands are expanded by augmenting the elements in both the duplexer design and the RF power amplifier. This power amplifier was chosen for the specific frequencies of operation. The programmable filters, which reside on the system's analog side, simplify the demands on the ADCs and digital-to-analog converters (DACs).

This design uses a finite number of fixed bands and bandwidths. Yet it provides for a fully programmable baseband processor. In addition, it implements a version of SDR that has considerable benefits in terms of development cost and flexibility.

This version is particularly applicable to consumer and public-service/emergency applications. These applications support a limited number of operating modes from a single user terminal. Frequency assignments do not change quickly. As a result, the main issue is how to augment capacity and improve functionality within existing allocations.

Beyond the RF challenges, the increasing diversity in air interfaces is placing much greater demands on a wireless system's digital-signal-processing elements. It doesn't matter if these elements are DSP-, FPGA-, or fixed-logic-based. Air interfaces like GSM, ANSI-136, and EDGE typically require high-resolution processing in the 16-to-20-b range. In contrast, CDMA interfaces typically work at lower resolutions of 6 to 8 b but at much higher processing rates. The CDMA interfaces also tend to include numerous single-bit operations. This diversity in both bit widths and operation types severely strains any architecture that comprises homogeneous elements. To get even more complicated, the systems that support programmable RF bandwidths need to be flexible in filtering. This characteristic imposes even greater loads on the signal processing.

Three basic IC options exist for the baseband portion of an SDR system: DSP-based, hybrid DSP/FPGA systems, and adaptive/reconfigurable architectures. Fixed logic-based systems are not included in this list. By definition, they are not compatible with software-defined radio.

The DSP-based systems are well known and supported by mature tools. Generally, however, they lack the processing power needed to handle complex systems. While DSPs have recently reached a performance level that is adequate for GSM, the more complex air interfaces, such as EDGE, cdma2000, and W-CDMA, are well beyond what can be handled by DSP-only systems. To meet the cost, power-consumption, and performance requirements of consumer products, 80% or more of the signal processing will typically be assigned to more efficient ASICs.

The design flow that is used for DSPs is represented in Figure 2. The advantages to this approach are the homogeneous nature of DSPs and the maturity of the toolchain. By basing the system design on high-level design languages like C, the toolchain considerably simplifies the design process.

The problem occurs as DSP systems move into optimization to reduce power consumption and cost or meet minimum performance targets. At this stage, the designer must often resort to assembly-language programming. Such programming considerably increases the design effort. If multiple DSPs are required, the integration becomes much more complex. The tools for this task are less mature and sophisticated. Typically, they are specific to the implementation.

Banks of high-powered DSPs can be useful in a prototyping environment. Yet a homogeneous architecture of one or more DSPs falls far short of the performance needed for SDR systems. Usually, at least some algorithms have to be prototyped in FPGAs or ASICs. In addition, this approach would fail to meet the cost/size/performance expectations for consumer and commercial systems.

Due to DSP design limitations, designers have had to augment DSPs with FPGAs when building SDR systems for complex air interfaces. In this hybrid design, FPGAs are typically used to implement the front-end downconversion, filter, and demodulator functions (FIG. 3). The downstream processes are passed off to the DSPs when the processing rates reach a level that a DSP can handle. DSPs also may use FPGAs as configurable co-processors. They will handle some of the functions that do not fit well on the DSP, such as code generation.

Figure 4 shows the design flow for a hybrid system of DSPs and FPGAs. In this flow, system engineering and partitioning play a major role. It is critical for the elements to be properly mapped to either DSPs or FPGAs. It also is vital that the interaction between the two worlds is well understood and implemented. Otherwise, the DSP or FPGA material may be significantly underutilized. One resource will then stall while the other completes its task.

To further complicate matters, the DSP design uses a software design flow while the FPGA design uses a hardware design flow. There is little overlap between the skill sets of the relevant design teams. Often, these teams are isolated by the differences in their skill sets. Their limited interaction hinders the possibility of significant design improvements at the system level.

Linking the two systems is even more complex. Typically, these hybrid systems are built up at the board level from a multiplicity of ICs from various vendors. As such, design environments that integrate both DSPs and FPGAs are very limited in functionality—if they're available at all. The high-level abstractions that are used for communication between the FPGAs and DSPs are practically nonexistent. A lot of engineering effort is therefore spent building up communications between the various elements. This difficult and exacting process adds little practical value to the overall system.

Usually, hybrid designs are only implemented at the board level. This fact significantly impacts the application of these systems. Although the issues here are more business-related than technical, the barriers are just as real. Relatively little open-market IP is available in the FPGA-core and DSP-core domains. The IP that does exist resides with the big semiconductor companies like TI, Altera, and Xilinx.

Hybrid FPGA/RISC designs are beginning to appear. For third parties, though, it is very difficult and time consuming to develop and integrate an SoC-based design using open-market DSPs and FPGA material. Inevitably, business relationships will form to somewhat ease this situation. Most likely, however, this will occur only within the domain of the major IC houses.

Whether they are fine- or coarse-grained, homogeneous FPGA structures tend to map inefficiently to all but the simplest of problems. As a result, the typical gate-utilization numbers are well below 10% for FPGA material. The large amounts of interconnect and corresponding drivers result in power consumption that is well above the consumption of a typical ASIC-based design. This factor is critical for handheld devices, which hail battery life as their king. The same can be said of handheld users. Consumers are already voicing expectations for talk and standby times that are only met by state-of-the-art ASIC/DSP designs.

Board-level hybrid designs are not viable for handheld mobile/wireless devices. The physical size, power consumption, and high cost of such designs restrict their use to high-end, wall-socket plug-in systems. These hybrid systems are well outside the envelope of a consumer product. Even with the use of 'future' SoC hybrid designs, power consumption and cost points will remain well above consumer-product targets. The problem is the FPGA material and its inherent inefficiencies.

Hybrid DSP/FPGA designs can certainly overcome some of the limitations of DSP-only designs. Yet they also introduce cost, size, and power-consumption issues. These issues preclude their use in many consumer applications.

Increasingly, people have begun to recognize the limitations of DSPs and DSP/FPGA hybrid designs. As a result, a number of startup companies have been founded on the concepts of adaptive and reconfigurable computing. Typically, the architectures for these IC technologies use coarse-grained computational units with a programmable-interconnect structure.

In this context, reconfigurable is used to describe a hardware design in which the datapaths and computational units are configured into a fixed configuration. They are only reconfigured at the major inflection points in processing, such as the changing of a mode of operation. Typically, reconfiguration requires that processing be stopped for a large number of clock cycles while the operation is performed. The latencies that are associated with reconfiguration tend to preclude changes "on the fly." As a result, designers are forced to use the system in a linear dataflow manner. They process data at the input rates of the system.

For the circuits in reconfigurable systems, this means that they typically run at a few 10s of MHz. They waste the capability of transistors, which may be capable of running at 500 MHz or more. The overhead associated with the programmability, when combined with the slow processing rates, results in designs that are larger than ASIC- and DSP-based designs. Once the designer gets into multi-mode operations, the flexibility offsets the overhead. For example, Intel recently set its break-even target for reconfigurable architectures at three modes.

The above discussion also applies to FPGA-based designs. In these designs, real-time reconfiguration is difficult. The problem is the large number of bits needed to reprogram the structures as well as the latencies associated with loading these bits.

Recognizing these limitations, adaptive-computing architectures have stepped in to overcome the reconfiguration latencies. By changing architectures on the fly, at run time, and in as little as a single clock cycle, they vow to free computational units from the limitations of linear dataflow. Essentially, they permit them to run at optimized processor speeds.

Figure 5 depicts Quick-Silver Technology's Adaptive Computing Machine (ACM). Using homogeneous interconnect structures, this architecture ties together heterogeneous computational units. The internal functions and datapaths of these units are adapted clock cycle by clock cycle. When freed by the internodal interconnect structure and internal memory, these computational units or nodes eliminate the need to process data synchronously. They may then run at processor speeds that are typical of best-in-class DSPs.

Being heterogeneous in nature, however, the ACM is not burdened with the overhead of inefficient structures. It also does not need to process instructions to complete tasks. As a result, the ACM is designed to be much more efficient in size and power consumption than a DSP.

Figure 6 illustrates the design flow for adaptive computing. The designer starts with a high-level system model. That model is divided into algorithmic elements that are consistent with the system's signal flow. Next, these individual elements get mapped to the heterogeneous node types through a mixture of high-level and assembly-language programming. Judicious use is made of the preprogrammed modules. By using heterogeneous structures, the designer can more closely match the algorithm to the hardware elements. As a result, he or she can develop a lower-power-consumption, lower-cost design.

The communication between algorithmic tasks and the assignment of tasks to individual node instances are both abstracted in a high-level language and through operating-system calls. The same is true for nodal multi-tasking. With this design flow, the developer can focus on optimizing the algorithmic elements. He or she can reallocate and re-map resources as the system is assembled and final computation requirements are determined.

The result is a diversity of computational units that are assigned to a multiplicity of tasks. For an IC designed for a handheld device, this translates into greatly increased efficiency. With this rising efficiency, even single-mode ICs based on adaptive computing can make economic sense. In this environment, the architecture flexibility translates into multi-mode operation. It also offers the ability to evolve or change the functionality over time, thereby casting a much broader application net.

The inherent, flexible nature of adaptive-computing architectures holds great promise. These architectures may be able to deliver SDR platforms for the consumer market. Such platforms will offer low cost, low power consumption, and high performance.

Currently, most commercial/military SDR system development is based on hybrid designs of off-the-shelf DSPs and FPGAs. The applications for these hybrid designs include cellular base stations and military SDR platforms. Such applications are not constrained by low-power-consumption requirements. Typically, they use numerous boards of such designs to achieve a high degree of programmability and performance. In these low-volume applications, the maturity of the toolchain and the availability of off-the-shelf software modules tend to play a key role. After all, NRE development is a significant per-unit cost factor.

Thanks to the broad usage of DSPs and FPGAs in the wireless arena, a fairly substantial base of DSP modules exists. These DSPs run on the above platforms with minimal modifications. With reasonable effort, systems can be assembled that meet the needs of a certain class of customers. The drawback is that these designs tend to be very large, power hungry, and expensive. Against the backdrop of the multi-terminal alternatives, however, they are attractive.

Another approach might be custom silicon that is specifically designed for SDR applications. In general, though, this approach has met with minimal success. The low volumes add up to high per-part cost. In addition, the toolchains remain underdeveloped and the available module libraries are very limited. Custom silicon does offer benefits by using a more efficient architecture. But these advantages are offset by the difficulties in development.

The companies that are focused on adaptive computing are working to overcome the limitations of custom silicon. Specifically, they are targeting the low-power, high-performance space of the mobile- and wireless-device consumer markets. Given the volumes of these markets, it is possible to justify the investment needed to provide an efficient toolchain. These markets also welcome the "all-software" development models that are familiar to the DSP community. Indeed, adaptive computing may reset current paradigms for SDR platform development. It just needs to overcome the performance/cost limitations of hybrid DSP/FPGA designs. In addition, it must provide for a homogeneous software-based design environment.

The demand for SDR will significantly increase over the next several years. Just look at the development costs for custom silicon. This silicon is the basis of most cell-phone designs. Now, it is becoming too costly for all but the largest manufacturers. Software-defined radio also can mitigate the transition issues that are associated with the migration to third-generation (3G) and more advanced systems.

The current emphasis on national security also must be taken into account. It will only increase the demand for interoperable communications in the government and military sectors. SDR provides one of the few mechanisms for interoperability without performing wholesale replacements of existing systems. Plus, SDR permits multi-mode operation that reduces the degradation in fixed systems. The software can just switch to alternative communication channels.

Clearly, the wireless- and mobile-device markets are rapidly moving to adaptive and reconfigurable technologies. Pioneering efforts have been made by several startups. Now, many of the old-guard semiconductor companies are announcing their own research programs. Even they are endorsing the reconfigurable and adaptive concepts.

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