The world of wireless communication is very segmented. For example, varied communication standards exist in different regions of the world. Each of these standards is mandated either by governmental regulation, historical technological infrastructure, required data rates, or a lack of alternatives.
In the wide-area-network (WAN) space, the breadth of current 2G standards includes GSM, PDC, TDMA, PCS, and various versions of CDMA. For wireless local-area networks (WLANs) and personal-area networks (PANs), the dominant standards in existence are IEEE 802.11a, IEEE 802.11b, and Bluetooth. Though these standards are meant to utilize unlicensed frequency bands, their existence becomes complicated. Not all of these standards are regulated in different parts of the world.
Yet no matter which standard exists—in an area, for an application, or for whatever reason—the trend toward convergence is ongoing. It is now forcing wireless-device designers to supply products that are capable of supporting more than one standard or frequency band. This pressure is being passed down to integrated-circuit (IC) designers, who design the transceivers that establish and maintain the physical connections between wireless-capable devices. These designers also are being pressured to supply increasingly affordable products for consumers. This issue is causing IC designers to rethink their traditional architecture of choice.
Into this picture enters the direct-conversion architecture for transceiver design. Historically, most wireless-enabled devices have utilized the superheterodyne architecture. This choice was largely made because direct conversion has traditionally had design and production difficulties. These difficulties hampered its adoption into wireless devices. Some firms have solved these design difficulties, however. They are now producing transceivers based on the direct-conversion architecture that are more cost effective than superheterodyne. As such, these transceivers are more suited toward multiband and/or multimode solutions.
The typical block-level diagram for a wireless radio receiver is shown in Figure 1. Although this structure has often been associated with the superheterodyne architecture, different proprietary advancements in design have blurred the boundaries between this and other architectures. The direct-conversion architecture utilizes a similar format with the exception of the intermediate-frequency (IF) stage. This stage is shown between the two phase-locked loops (PLLs) of Figure 1.
The superheterodyne-based receiver accomplishes all filtering with passive components. It is characterized by two downconversion processes. To be demodulated, these processes produce a baseband signal. The direct-conversion architecture, on the other hand, requires only one downconversion process. It performs its channel filtering by utilizing a low-pass filter.
Some applications require a low-IF solution to be used instead of a direct-conversion solution. The difference between the two is that a low-IF structure has a superheterodyne receiver coupled with a direct-conversion-based transmitter. Because of their overall flexibility, however, true direct-conversion architectures are more preferred by IC designers.
In the signal-reception stage, the radio transceiver amplifies the radio-frequency carrier signal. It then translates and filters that signal to produce the baseband signal. Some of these functions can be accomplished via a digital design. But by and large, most of them are accomplished via an analog design.
After the RF signal is received by the antenna and filtered, it is amplified to meet the dynamic range of the RF system and block out extraneous noise. The total amplification process is performed via a low-noise amplifier (LNA) and a variable gain amplifier (VGA). The LNA is chosen according to its linearity and noise figure, while the IF amplifier is valued for its gain control. When multimode and multiband solutions are considered, the LNA can cover entire bands with minimal hardware overhead. The filtering is required if the desired channel data is going to be selected by suppressing any interference.
The frequency translation is complicated. It is only done with ease because of a function of the channel spacing of the particular wireless standard. For GSM, 200 kHz of channel spacing is required. CDMA requires 1.25 MHz. The integrated phase-locked-loop devices are usually designed to support all required channels. The voltage-controlled oscillator's (VCO's) operating range should be designed to be wide enough to cover the entire operating frequency range. The phase noise should be small enough to eliminate spurious mixing with nearby interference.
The selectivity depends upon the frequency location and channel bandwidth. As the frequency increases and the channel bandwidth is reduced, it becomes difficult for integrated devices to effectively perform the channel-filtering function. In order for a superheterodyne-based system to filter between the RF and IF stages or reception, a passive component is normally utilized. An example is a surface-acoustic-wave (SAW) filter.
Most of the hardware following this channel-selection filter has loose linearity requirements. For instance, say the channel-selection filtering is done quite close to zero frequency or at the baseband in a direct-conversion transceiver. The filter can then be designed utilizing silicon devices and passive elements, such as resistors and capacitors. A low-quality low-pass or bandpass filter may be used in this instance. Yet all of the building blocks—including the channel-selection filter—should have a dynamic range that is high enough to survive the strong interference effects.
In a multiband or multimode RF system, it is difficult to design a receiver structure that has the same structure as the one discussed above. The main design objective is to minimize the overhead in hardware. Ideally, then, each functional block should support as many of the communication standards or frequency bands as possible.
Highly linear and low-loss front-end bandpass filters are typically used at specified bands. They can therefore reject the wideband out-of-band interference. Such interference usually requires signals that are stronger than the desired signal by 70 or 80 dB.
The number of passive filters depends on the technical-challenge level of each standard. The narrowly tuned low-noise amplifiers, which follow each front-end filter, help to suppress out-of-band interference. The key issue with wideband amplifiers is that each tuned amplifier should cover each specified band. The number of amplifiers and the operating bandwidth of the tuned amplifiers are essentially the designer's choice.
The most critical element is the channel selection, as it may be bulky and thus occupy most of the die or printed-circuit-board (PCB) area. The direct-conversion radio receiver incorporates the adjustable channel-selection filter of low-pass type (FIG. 2). The modern high-end integrated filter can provide the IIP3 with more than 30 dBm. It is therefore unlikely that it will limit the dynamic range of the system. To achieve a design margin for mass production, however, innovative gain control and DC-offset handling algorithms are required.
Referring back to Figure 1, the front-end gain control in the LNA helps to optimize the noise figure and linearity. In this scenario, the dynamic change of carrier leakage or DC offset during gain control should be carefully handled. It must not corrupt the signal and produce unwanted transient behavior. The adoption of the innovative gain control and the DC-offset handling algorithm is highly recommended when considering low-cost CMOS technology for cellular applications.
Those algorithms are all platform independent. To increase performance, they can be used in any other process technology. The channel-selection filter can be easily adapted by changing its cut-off characteristics. Yet some algorithm calibration is required to correct gain imbalance and phase mismatch in the I/Q path.
For example, the gain imbalance should be less than 0.5 dB to support the full data rate of 54 Mbps as defined in the IEEE 802.11a standard. This value is hard to achieve without a special technique that considers the production yield.
The channel filtering also may be partitioned into analog filtering and digital filtering, depending upon the required attenuation, signal-to-noise ratio (SNR), and channel bandwidth. When digital filtering is considered, the resolution of the analog-to-digital converter (ADC) should also be taken into account. In the case of narrow channel spacing, a state-of-the-art ADC can achieve more than 15-b resolution with very small power consumption. This kind of implementation is attractive for GSM applications, in which the channel spacing is only 200 kHz.
Digital low-IF transceivers are commercially available for the GSM cellular market. But the digital low-IF receiver is not universal, as it cannot cover the standard's large channel spacing. Instead, the low-pass filter with adjustable cut-off characteristics offers a simple way to achieve target performance.
The largest design barrier for a multimode and multiband design is the inclusion of a PLL with superior performance and a wide operating range. In a multiband design, the frequency planning for the LO signal is a difficult but necessary task. It is needed to minimize the number of VCOs. Those VCOs are required to cover the entire operating range. The LO signal can be sourced from either a sophisticated mixer structure or a LO generator. When utilizing the direct-conversion architecture, remember that a low-carrier leakage level alleviates the DC-offset problem (FIG. 3).
The synthesizer in the PLL plays an important role in carrier signal generation. After all, its resolution limits the allowable channel spacing of the PLL. To cover a broad range of applications and reference-clock sources, use an inherently low resolution for the frequency spacing. The sigma-delta synthesizer is becoming more popular in the design world for this specific purpose. It boasts fine resolution of up to 1 Hz. The design caveat, however, is that the loop bandwidth and linearity of the phase-locked loop should not produce spurious tones.
Quite a few companies are working to address the design topics discussed in this article. For example, the efforts of GCT Semiconductor are currently focused on refining the robustness of its patented direct-conversion architecture. At the same time, GCT is working to improve the circuit design of the functional blocks described previously. It also is rethinking the algorithms that were mentioned.
The company's first-generation transceiver chips, which support the Bluetooth standard (IEEE 802.11b), have already adopted these key technical achievements. For proof of the evolution of multimode and multiband transceiver development, look to GCT's PLL design, including its synthesizer architecture. The DMPLL technology uses the sigma-delta synthesizer as the core. It solves the tone-generation problem through progressive circuit-level design and algorithm development.
WRAPPING IT UP
In the wireless-device industry, current design and marketing trends are pushing RF circuit designers to adopt alternative RF architectures. They are being called upon to use forms of the direct-conversion architecture. Com-pared to its dominant predecessor—the superheterodyne architecture—the direct-conversion architecture is more cost effective for single-band, single-mode designs. This benefit is magnified when considering the architecture for multiband and/or multimode designs.
Though technical design challenges will surely accompany these next-generation chip sets, many companies are already working hard to address such issues. In the days ahead, it's a sure bet that these companies also will be working on bringing innovative solutions to some long-standing problems in the wireless-communications industry.