Suffering From the Jitter Bug?

Signal sources can help predict serialiser and deserialiser jitter behaviour.

Signal jitter is one of the more difficult compliance issues confronting serial device designers. With their high data rates and embedded clocks, modern serial devices can be susceptible to jitter that degrades biterror rates. Industry-accepted methods for specifying jitter tolerance can't always pinpoint certain types of failures, particularly frequency-dependent jitter.

Most serialiser/deserialiser (SERDES) device specifications define values for both deterministic and random jitter tolerance. Deterministic jitter relates to repetitive events occurring in the environment; for example, the operation of a switching power-supply oscillator. Random jitter arises from uncorrelated causes both inside and outside the system.

Most SERDES devices exhibit more susceptibility to deterministic jitter as jitter frequencies increase. The amplitude and frequency of clock jitter can also dramatically effect jitter tolerance. The best approach is to characterise frequency-sensitive behaviour in advanced and select SERDES components whose jitter performance is compatible with the other larger design goals.


Clock jitter and data jitter each play a role in SERDES bit-error rates. Jitter in the system clock, and how the PLL handles it, is a key factor. The PLL tends to transfer incoming jitter to its output, with certain variations that depend on the jitter frequency.

Low-frequency behaviour: Jitter causes individual data samples to shift from their ideal placement in time. In an oscilloscope eye diagram, this manifests itself as a "closing" of the eye. That is, errant bits taint the area that should be open. However, in lowfrequency situations, many SERDES devices can adjust the sampling point to ensure good data capture. Thus, they can track jitter amplitudes equivalent to many bit times in some cases.

Intermediate (mid) frequency behaviour: Interactions in the intermediate-frequency range tend to be complex. In this range, both clock and data jitter contribute to the whole. The PLL passes some clock jitter to the sampler, and jittered data enters the sampler as well.

High-frequency behaviour: Because clock jitter has little impact at high frequencies, analysis should focus on the data's jitter content, once the clock jitter frequency crosses over to the descending portion of the PLL jitter- response curve. The sampler no longer tracks eye movements in this jitter frequency range. Rather, the overall integrity of the eye diagram is the determining factor. The sampler will capture data correctly as long as the eye stays significantly open.


Jitter testing relies on applying modulation to the data and clock signals feeding the SERDES under test. One important characteristic of jitter is its "profile." This is the shape of the modulating waveform, and it affects the shape of the histogram that results when measuring jitter. Profile types include Gaussian, sine, square, triangle, random, and more. For a given eye opening, the jitter profile has a significant effect on biterror rate (BER).

The sine and triangle are the two predominant shapes used in jitter-tolerance testing. Both histograms display a relatively rectangular area under the curve, as opposed to the more pointed peaks of the other profiles. The SERDES sampler seeks the median of the rectangular region and attempts to place the latch sample window at the 0.5 UI from the median.

The sinusoidal profile, in common use throughout the industry, makes a good example for discussion here. The jitter measurement procedure consists of connecting discrete sinusoidally modulated jitter sources to the SERDES reference clock and serial data inputs, adjusting the two sources independently for jitter amplitude and frequency, and monitoring the output for bit errors.


Generating jitter is a task that demands well-integrated, compatible tools. The signal requirements are stringent. The bandwidth and accuracy of the data/timing source must be compatible with the multi-gigabit data rates used in today's serial devices. The source of the clock and data-signal jitter should be independent of the oscillator that generates the actual clock and the data signals.

In addition, the jitter on the clock and data should be independent (not phase-locked) and the two signals should be controlled separately. Lastly, the amplitude and frequency variation in the jitter should span a large range.

Sine-wave generators (modulation source)>: The sine-wave generator may have two discrete outputs. Alternatively, two generators can be used. The frequency of the sine wave determines the frequency of jitter on the modulated signal. Its amplitude sets the amplitude of the jitter on the signal.

Data timing generators (clock and data source): Working handin- hand with the sine-wave generator is a digital signal source, such as the Tektronix DTG5000 Series Data Timing Generator system. With DTGM31 Jitter Generator modules installed, it can accept the two modulating input signals and apply their effect to the serial pattern data. The module's two independent outputs provide a jitter-modulated signal in proportion to the sinewave input (Fig. 1).

Bit-error detection: On the acquisition side, bit errors from the SERDES may be detected using either a logic analyser or a biterror- rate tester (BERT). The logic analyser triggers on errors and acquires parallel data from the SERDES, while the BERT acquires serial data from the SERDES. The BERT compares its acquisition with the reference pattern coming from the data generator.

DSOs: A digital storage oscilloscope can measure actual peak-to-peak jitter amplitude values once it's determined that bit errors occurred, and it can display the all-important eye diagram. Some oscilloscopes can be optioned with integrated jitter-analysis software tools to dramatically simplify these various tasks.


Figure 2 provides a simplified view of a procedure used to measure and document jitter behaviour in a SERDES. "Typical" values are shown here, but individual users will choose parameters based on the characteristics of the device under test. The illustration depicts only the data-jitter portion of the test. However, the clock-jitter process follows the same steps while holding data jitter constant.


Results are best presented as a series of curves, with each curve representing the amount of data jitter the SERDES can tolerate for a particular value of clock jitter. The clock jitter (amplitude and frequency) is held at a fixed value for each curve. The clock-jitter frequency is the x-axis and the jitter amplitude is the y-axis.

The curve is generated by increasing the data jitter's amplitude to determine the highest value at which the part passes, producing no bit errors for a specified time. Separate graph traces represent differing frequencies and/or amplitudes of clock jitter. Figure 3 shows two curves plotted in this manner.

Frequency-dependent jitter is a factor in every SERDES' performance. Jitter-modulated stimulus signals can help designers characterise SERDES jitter behaviour and avoid the design problems that result from selecting a component with incompatible performance.

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