Trio Of Chip Introductions Solves Contemporary Clock Issues

The Octeon network service processors come with two, four, eight, or 16 MIPS processors. The devices also may be cascaded to further improve performance.

Designers used to take the clock circuit in digital systems pretty much for granted. But speed-enriched systems that must work with multiple communications standards have turned the innocuous circuit into a major design hassle. Three new clock chip varieties from Maxim Integrated Products address these design problems.

The MAX9489 network clock generator targets a variety of communications and networking applications, including network/edge routers, telecom/networking equipment, and data-storage systems. It has multiple outputs and exhibits high performance with low jitter and minimum skew. Also, it generates 15 independently programmable clock outputs.

Each single-ended low-voltage transistor-to-transistor logic (LVTTL) output can be set to one of 10 common clock frequencies: 133, 125, 100, 83, 80, 66, 62.5, 50, 33, or 25 MHz. The clock is programmable via an I²C serial interface. The frequencies are derived from an external 25-MHz crystal. Output period jitter is less than 48 ps rms, and output-to-output skew is less than 200 ps.

This chip comes in a 32-lead 5- by 5-mm QFN package and operates from ­40°C to 85°C. Required power is 3 to 3.6 V, with a typical power dissipation of 450 mW. Prices start at $6.77 for 1000-unit lots.

Next are the Dallas Semiconductor DS26502/DS26503 64-kHz clock transceivers. The DS26502 building-integrated timing supply (BITS) clock-recovery circuit supports popular clock frequencies, such as the 64-kHz timing interface, the 2048- and 6312-kHz Japanese synchronization interfaces, and the standard T1/E1/J1 interfaces. Basic framing and formatting also are provided in the T1/E1/J1 operating modes, bringing versatility and low cost to composite clock and T1/E1/J1 architectures.

Basically, the DS26502 can translate from any of the supported inbound synchronization clock rates to any supported outbound rate. No external component changes are required to switch between any of the basic sync clock rates or the T1, E1, and J1 standards. No relays or switched external components are required, and a single master clock supports all operating modes.

The DS26503 is identical to the DS26502 except for the 64-kHz composite clock capability. Both chips come in a 64-pin LQFP package and are available in commercial (0°C to 70°C) and extended (­40°C to 85°C) temperature ranges. Cost is $16.85 for the DS26502 and $11.80 for the DS26503, both in 5000-unit lots.

The third new entry, the MAX9486 clock chip, is designed for T1, E1, T3, E3, and ADSL/VDSL applications like line cards and related equipment. It uses an external 17.664-MHz crystal and an 8-kHz input reference clock to generate six identical buffered LVTTL clock outputs at 35.328 MHz (see the figure). The internal clock phase-locked-loop voltage-controlled crystal oscillator can track the input reference by ±200 ppm. A low-jitter 8-kHz clock output is used as a reference clock for other parts of the system.

The MAX9486 can detect the absence of the input reference clock and lock to the output clock to 35.328 MHz, with an accuracy of ±25 ppm. The circuitry also uses the 8-kHz input clock and synchronizes it with the multiple buffered outputs from 15 to 78 MHz. In a 24-pin TSSOP package, the chip goes for $6.14 in 1000-unit lots.