EE Product News

Chip Synthesizes Clocks For WANs

Capable of simultaneously synthesizing two output clocks synchronized to a reference clock, the XRT8001 dual phase-locked-loop chip has a new ST Bus-class capability that permits it to support higher frequencies for WAN and ISDN applications. The chip can synthesize two low-jitter clocks with standard frequencies, phased-locked to the system reference timing, enabling it to accept a wide range of popular telecomm and networking input frequencies: 8 kHz, nx56 kHz, nx64 kHz, nxT1 and nxE1. It also can be programmed to generate a range of output frequencies: 1.544 to 2.048 MHz, as well as 1, 2, 4 or 8 times 2.048 MHz. The XRT8001 industrial-temperature-range chip comes in 18-pin SOICs and PDIPs.

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