Electronic Design
Crystal Oscillators Evolve To Meet High-Speed Networking And Storage Needs

Crystal Oscillators Evolve To Meet High-Speed Networking And Storage Needs

Crystal-quartz oscillator technology has dominated the world market since World War II, when engineers used them as frequency-control devices. Its superiority continues today, despite the arrival of other new timing reference technologies, such as surface acoustic wave (SAW) and microelectromechanical systems (MEMS).

Like any other device, the basic requirements of a crystal oscillator (XO) are manufacturability, low cost, stability, and reliability. Those features lie at the heart of these devices, offering a solid, competitive price/performance ratio for applications in networking, RF/wireless, CPUs/microprocessors, and other ASICs.

To maintain resonance of the quartz piezoelectric property, electrical circuits must provide synchronized energy to compensate the loss during oscillation. One of the most popular circuits in this case is the inverter crystal drive circuit (Fig. 1).

The crystal vibrates and produces a steady oscillation when it’s excited with a maintenance voltage. The mode of vibration depends on crystal cuts, such as thickness shear for AT and BT cuts. Typically, the higher vibration frequency requires a thinner crystal cut. However, the thinner crystal creates challenges in terms of manufacturing and reliability.

Popular XO Technologies

Third-overtone XO: To overcome the challenges inherent in high-frequency quartz—a necessity in today’s high-speed electronic applications—there’s the third-overtone XO. It offers a similar crystal drive circuit diagram to that in Figure 1, but adds a special inverter amplifier that makes the crystal vibrate on its third tone mode only. Figure 2 illustrates the crystal reactance curve of the third tone.

Analog-multiplier XO: For today’s manufacturability, the maximum fundamental mode crystal can go up to 50-MHz frequency. Therefore, the maximum third-overtone XO (3OT XO) frequency can reach 150 MHz. To meet XO application requirements over 150 MHz, patented analog-multiplier XO technology can boost the 3OT XO to approximately 250 to 300 MHz with performance comparable to a single XO (Fig. 3). It has a direct frequency multiplier stage following the third OT XO circuit.  

PLL XO: To achieve a frequency oscillator that goes beyond 250 MHz with a lower-frequency fundamental crystal, designers can apply PLL XO technology. Replete with a phase-locked loop (PLL) following a fundamental crystal oscillator, it delivers crystal stability and reasonable phase noise to meet application requirements of high-speed networking and storage serial connectivity (Fig. 4). Of course, the final oscillator performance depends heavily on the PLL’s performance. One can opt for a different PLL voltage-controlled oscillator (usually a silicon VCO), such as a ring-type oscillator or LC tank oscillator. Overall, the PLL XO can reach frequencies of 1 GHz or higher.       

Two types of XO output buffers are used for these technologies: single output (CMOS and TTL) and differential output (LVPECL, LVDS, and HCSL). A single output is simple to use with bigger voltage swing, but it doesn’t have good noise immunity for longer PCB trace lengths (Fig. 5). Sometimes, it may develop EMI issues for its larger voltage swing. Nonetheless, a single-output XO is usually more economical in price due to simpler manufacture procedures and cost.

Differential output can overcome single-output disadvantages because it is standardized. LVPECL, LVDS, and HCSL are typical differential-output single-ended voltage levels (Fig. 6). In general, a particular differential-output buffer should match the particular receive requirement. It’s worth noting that each differential output has its own external termination scheme, which needs to be checked in the application.   

Application Benchmarks

Phase-noise RMS jitter, period jitter, and power-supply noise rejection (PSNR) represent general application benchmarks.

Phase noise: XO frequency noise is depicted as phase noise (the final noise from the XO device), and is expressed as a function of frequency offset from the output frequency. It’s measured as power ratio between the carrier frequency and its frequency offset noise spectrum normalized in 1-Hz bandwidth.

Take, for example, Agilent’s E5052, which is used to measure a 62.5-MHz 3OT XO phase-noise plot (Fig. 7).  The “-146.3955dBc/Hz” at 10 kHz means a -146.39-dB ratio of carrier power to the noise power at 10-kHz frequency offset from the carrier in 1-Hz bandwidth. By integrating phase noise in a certain frequency bandwidth, such as from 12 kHz to 20 MHz, phase-noise RMS jitter for that carrier is obtained. The phase jitter for the 62.5-MHz 3OT XO is 100.11 fs.  

Different applications have different phase-noise requirements. For higher-frequency XOs, applications such as the Serial Attached SCSI (SAS) serial link care about the phase jitter (approximately 12 kHz to 20 MHz) due to their SERDES bandwidth-reference frequency-tracking characteristic. Less than 1 ps of RMS phase jitter is a general requirement.

Different types of XOs have their own phase noise due to the technology employed.  Figure 8 compares three types of XO phase noise plots.  

Period jitter: Period jitter, which looks at XO jitter in the time domain, is measured as peak-to-peak jitter. It is also measured randomly in certain sample lots (1k to 10k) per test; tests are accumulated to the specified size (20k to 100k) to achieve the final period peak-to-peak value. In this way, the test equipment’s local jitter can be maximally eliminated from the tested XO. To illustrate, Wavecrest’s DTS-2079 period jitter test set reveals the peak-to-peak period jitter of Pericom’s FN series 62.5-MHz 3OT XO (TJ = 30.049 ps, RJ = 2.162 ps, and peak-to-peak =18.10 ps) (Fig. 9). This device suits SATA/SAS hard-drive applications that require very low period jitter.  Table 1 compares the period jitter for the three types of XOs.

PSNR comparison: In high-frequency serial connectivity applications, one major concern is an XO’s power-supply noise immunity reflecting to output frequency jitter. To benchmark different XO PSNR capabilities, the DUT is tested in the same power-noise injection setup; for example, inject a -30-dBm power sinusoidal signal (with swept frequency) onto the power rail and record the carrier versus reflected phase-noise spur in dBc. Figure 10 compares general PSNR for the three types of XOs.

PCIe XO Application Example

The PCI Special Interest Group (PCI-SIG) has specified the PCI Express (PCIe) 1.0 and 2.0 reference clock’s jitter budget for the PCIe common clock system architecture1,2,3. Perusing the PCI Express reference-clock requirements, PCIe 2.0 has a more stringent jitter requirement compared to PCIe 1.0, owing to higher serial frequency of 5 Gbits/s instead of 2.5 Gbits/s (Table 2). Several developments have arrived to address these stricter requirements, such as Pericom’s SHA000001 XO. It features a very small jitter clock source, which will be able to handle the coming PCIe 3.0 standard’s higher data rate and smaller system link UI jitter budget.

The PCIe 2.0 reference-clock measurement test setup4 is the same as PCIe 1.0, according to PCI-SIG specification (Fig. 11). PCIe reference-clock jitter test data is integrated with Intel’s clock jitter tool software5 to obtain the jitter value, using the following three-step procedure:

1. In Figure 11’s test setup, use the approved Tektronix scope (for example, Tektronix’s DTS7404) to take the 1 million clock cycles and record the cycle trend data as shown:

9.988888888885945E-9
9.975000000040507E-9
9.986111111095174E-9
9.98055555551363E-9
1.0008333333421347E-8
9.981250000015533E-9

2. Load this scope cycle trend data to Intel’s PCIe jitter compliance jitter tool software and run the Refclk jitter test in the selected jitter template profile (Fig. 12). Below is the Refclk jitter template example of PCIe 2.0 at 8 MHz, 1.5 MHz, and first order:

PCIE_2_0_8MHZ_1_5M_H3_FIRST: 

  •  
    • Clock Interval: 10 Nanoseconds
    • Jitter Budget: 27.9 Picoseconds
    • Expected Sample Size: 1 Million unit intervals
    • Expected Measurement Point: System Board PCIE Connector
    • Worst Case System PLL 1 (H1)                               
      •  16 MHz Low Pass. 
      •  40 dB/dec rolloff
      •  Damp = .54.
      •  Delay = 0.        
    • Worst Case System PLL 2 (H2)               
      • 8 MHz Low Pass. 
      • 40 dB/dec rolloff
      • Damp = .54.
      • Delay = 12 Nanoseconds
    • Minimum CDR  (H3)                                                 
      • 1.5 MHz High Pass. 
      • 20 dB/dec rolloff.
    • SSC Separation            YES

 

Note: The PCIE_2_0_8MHZ(BETA)_1_5M_H3_STEP template has the widest jitter pass band, which generates the largest PCIE_II jitter value for the same clock-cycle trend data.

3. Test the example of Pericom’s PCIe 2.0, 6-pin, 100-MHz XO, Part# SHA000001 jitter plot (Fig. 13). In this case, the tested SHA000001 exhibited an RMS jitter 1.82 ps (Fig. 14). Further information can be found at http://www.pericom.com/pdf/datasheets/se/290.pdf.

Table 3 summarizes XO frequency, output level, frequency tolerance, phase jitter, and period jitter requirements for different high-speed networking and storage standards. These include the Ethernet Passive Optical Network (EPON), Gigabit Passive Optical Network (GPON), Serial Attached SCSI (SAS), Serial ATA (SATA), 10-Gigabit Ethernet (10GE), 10-Gigabit Ethernet Passive Optical Network (10GEPON), 10 Gigabit/s Fiber Channel (10GE-FC), and PCI Express 2.0 (PCIe 2.0).

References:

1. “PCIe Base Specifications 1.1,” PCI-SIG, 2005
2. “PCI Express 2.0 Base Specifications Rev 0.7,” PCI-SIG 2007
3. “PCI Express Jitter Modeling,” PCI-SIG 2006
4. PCI Express testing with J.Bert N4903A, Agilent 2005
5. Intel Clock Jitter Tool 1.3 Release Notes, 2006.

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