Electronic Design

The Future Looks Bright For 3D Integration

In his comments at the 3D Systems Integration and Packaging Conference last month in Burlingame, Calif., Ho-Ming Tong, chief R&D officer and general manager of group R&D at ASE Group, quoted Victor Hugo, saying “You can resist an invading army, but you cannot resist an idea whose time has come.” Thus describes the general industry consensus that as scaling reaches its outer limits, 3D technologies will be set to take up the gauntlet of furthering Moore’s Law.

Frost & Sullivan included 3D integration in its latest Global Top 10 Hot Technologies to Invest. According to Kasthuri Jagadeesan, senior research analyst of technical insights at Frost & Sullivan, target market segments for 3D integration include CMOS image sensors (CIS), memory, processors, and FPGAs.

Further, Jagadeesan notes that with companies such as Intel, NEC, NXP Semiconductors, Tessera, Samsung, STMicroelectronics, and Amkor Technologies involved in driving the efforts in the 3D space, strategies such as application-centric collaborations exploring new applications could accelerate the commercialization prospects of 3D IC technology (Fig. 1).

Technologies that exploit the Z-direction have been around for quite some time, such as package-on-package, chip stacks with wire bond interconnects, embedded die, and fan-out and fan-in wafer-level packaging (WLP). Yet the challenge is finding the right method to achieve functional density at desired cost.

“It’s not going to be wire bond. It’s going to be TSV,” predicts Bill Bottoms, chairman of NanoNexus and iNemi. Through-silicon via (TSV) provides a shorter method of interconnect that allows for faster speed and lower power consumption.

Research by Yole Développment shows that despite a worldwide economic recession, the R&D activity linked to 3D companies has reached “unprecedented levels.” Jeff Perkins, general manager of Yole, predicts that 3D TSV technologies will be one of an assortment of offerings by 2015.

Perkins also describes a “3D packaging toolbox” that by 2013 will consist of 62% 3D TSV stacks, 18% 3D interposer modules, and 18% 3D WLP devices. He advises companies to pick their opportunities by looking for the ones that are trending toward 3D.

With regards to 3D TSV applications specifically, Jan Vardaman, president of TechSearch International, predicts timing for expected volume production by applications as:

  • CIS: volume production today
  • DRAM server applications: 2011-2012
  • DRAM with processor for wireless applications: 2012 and later
  • FPGA possible introduction: 2012-2013
  • Microprocessors with memory: possibly by 2014

“Our definition of volume production is being able to take a cell phone, laptop, what have you, tear it apart, and voila—find a TSV device inside,” Vardaman says. “It’s not a matter of doing the technology. It’s a matter of when it makes sense of adopting it in products.”

TURNING TO TSVS

For a long time, TSVs were considered too costly an option as a method of interconnect. Now we’re seeing them discussed as a cost-saving alternative. So what changed? Two things: the point of reference and the cost of manufacturing TSVs themselves.

The point of reference for cost comparison is whether you’re comparing the cost to wire bond or to the cost of scaling. TSV interconnects offer performance advantages in both realms. But while designers would switch from wire bond to TSV to improve performance, not save costs, TSV solves the density, performance, and cost issues when it comes to device scaling.

A year ago, the costs of ownership for TSV fabrication, wafer-thinning handling, design and test, and supply chain infrastructure were identified as roadblocks for market adoption of 3D TSV stacks. According to the foundries and packaging houses, much still needs to be done before marketable solutions emerge, although many developments in R&D are bringing things closer.

The EMC3D, a supplier-based consortium, reported achieving a TSV process flow at a cost of ownership (CoO) of less than $200/wafer last year. Having achieved that, the group set out to reduce it further to less than $150/wafer.

Rosalia Beica of member company Semitool reported at this year’s International Wafer-Level Packaging Conference (IWLPC) that the consortium has achieved further cost reductions in its process flows for both via first and via last approaches, and having reached the goal of less than $150/wafer, it is now targeting less than $120/wafer.

Thin wafer handling is of particular concern for 3D IC stacks with TSV interconnects. The overall solution for handling is temporary bonding to a carrier wafer to support the ultrathin wafer through backside processing, at which point the fully processed device wafer is debonded for the final stacking steps.

According to Bioh Kim, business development manager for EV Group, technology trends that address the challenges of the temporary bond/debond process are also emerging. He notes a shift in the adhesive materials from a laminate tape to a spin-coat adhesive; carrier wafer material from glass to silicon; and edge trimming for protecting the edges of the delicate wafers. Still to be addressed is standardization for bonded wafer pairs, including equipment specifications and carrier wafers.

Part of the delay with design tools, according to Frank Schellenberg, who monitors technology trends for EDA vendor Mentor Graphics, is that although 3D technologies are ready, there are too many options for designing. “Design automation means you need to figure out what you want to do and then automate it. It’s a fool’s errand to design an EDA tool before there is something to simulate,” he says.

Lisa McIlrath, president and CEO of 3D EDA vendor R3 Logic, concurs. “The roadmap is going to happen whether the EDA houses step up to the plate or not. If there’s an economic advantage to doing something a certain way, then people are going to do it, even if they have to rely on ad hoc ways to do it,” she says.

At a certain point, it gets too hard to continue using ad hoc approaches, and McIlrath says that time is now. The good news is that as customers are now calling for the required design tools, Mentor, Cadence, and Synopsis all say they’re working on solutions that will be ready in time for market adoption.

Due to the delicate nature of TSV chip stacks, external probe-based test equipment is no longer adequate for test because physical contact can disrupt and disguise characterization, validation, and test measurements to the point where real faults or failures cannot be distinguished from those anomalies introduced by the physical contact. As a result, the trend is turning toward embedded test and measurement instrumentation to verify and test devices from the inside out, rather than the outside in.

IDMs, FOUNDRIES, AND PACKAGING HOUSES

According to Jerry Bautista, director of technology management at Intel’s microprocessor research laboratory, the company is considering three different types of TSVs for three different functions: power delivery, thermal, and signaling.

“These require different materials and different aspect ratios for delivering different functions,” Bautista says. In other words, not all TSVs are the same. Overall, the word at Intel is that 3D stacking is still quite attractive and doable. But from a cost and implementation perspective, it’s going to take quite an effort, so Intel is still waiting for “the right product intercept.”

John Knickerbocker, distinguished engineering manager of system-on-package and 3D integration at IBM, notes that his company has been fabricating demonstrators of different applications to establish ground rules. He said IBM’s roadmap includes implementing 3D integration and optics to “derail the memory wall” and improve system performance.

“Assembly and test areas are in need of continued development in order to introduce 3D packaging in an efficient manner,” Knickerbocker says. IBM rolled out a simple TSV power amplifier in 2008. Not waiting for a specific product, rather he says IBM sees various platforms moving forward over time. It depends on the technology node and its sensitivity of risk aversion. Knickerbocker predicts 3D applications will roll out from 2012 and beyond or sooner depending on the application.

Douglas Chen-Hua Yu, senior director of the integrated interconnect and packaging division, R&D, TSMC, is forthcoming about TSMC’s plans for implementing 3D integration, the challenges faced by a foundry, and some of the supply-chain solutions the company has started to work out. Yu says it’s becoming clear that we’re nearing the end of Moore’s Law.

“It’s all about the economy,” he notes. “However, device performance and functionality is also a must.” He additionally emphasizes the need for a new business model that involves joint R&D and even production for wafer processing, substrate, and assembly. In this way, invested parties jointly manage the liability issue together.

Yu also says it’s important to filter through the many approaches available and choose a general one to focus on, then expand or add later. Ultimately, Yu says that regardless of whether you’re a foundry or an integrated device manufacturer (IDM), you need commitment, investment, and execution to secure success.

“Initial implementation of TSV in the OSAT infrastructure will likely take the route of interposer technology applied as an enhancement to prevailing package configurations, closely followed by via first with post-TSV processing managed by the foundry,” says Raj Pendse, VP of emerging technologies, STATS ChipPAC.

ASE’s Tong concurs, referring to that interposer step as 2.5D, bridging the gap because it’s closer to commercialization than full 3D IC and allows for device and function partitioning and the mix and match of packages. Meanwhile, industry innovation is still needed to reduce assembly cost.

“These things are happening now. These are being qualified by our customers,” says Ron Huemoeller, VP of advanced interconnect at Amkor. He also says that memory will be the next application to adopt TSV and that Amkor is working on a four-die memory stack with 50-µm die thickness, 10-µm diameter TSVs that will be available at the end of 2010 or early 2011 (Fig. 2).

The remaining hurdles are small, Huemoller says, and will work themselves out. He notes that assembly is not a hurdle in this space because Amkor can leverage known processes and equipment.

It’s clear that as the future unfolds, 3D IC innovations create a new marketplace. According to Tong, “You have a choice. You can be a believer, or you can be a nonbeliever.”

TAGS: Intel
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