NEW TECHNOLOGIES ENABLE MORE MOORE

Is the end near for Moore’s Law? Semiconductors are getting harder to scale due to thinner and closer wires that are getting hotter with higher impedances. Yet researchers are using carbon nanotubes (CNTs) to get around these limits.

James Jiam-Qiang Lu, associate professor of physics and electrical engineering at Rensselaer Polytechnic Institute, believes 3D wafer technology and the use of CNTs for interconnects will help semiconductor development maintain its current pace. Subhasish Mitra, assistant professor of electrical engineering and computer science at Stanford Univ., also believes transistors can be created using CNTs.

3D wafer technology attacks the interconnect problem headon as the speed of an IC has become a function of the length of the interconnect.

Bringing transistors closer together by stacking them would cut the delay time significantly. The idea is to take a base layer of silicon and layer other wafers on top in a pancake-stack configuration where various circuit elements form each pancake. The wafers are then bonded using inter-wafer interconnects.

While copper is the interconnect of choice now, it too may suffer from scaling issues. Lu also has researched methods of growing CNT structures vertically in a “forest” configuration that could be used for 3D semiconductor interconnects and other structures (see the figure).

“Carbon nanotubes are one of the most promising materials for interconnects in 3D integration,” Lu says. He has had to overcome CNTs’ natural tendency to grow sparsely when configured vertically, which leads to poor conductivity. Dipped in a liquid organic solvent like isopropyl alcohol, though, the CNTs become very densely packed for much better conductivity.

The next part involves the use of CNTs for the fundamental building block of ICs: the transistors. Yet CNTs tend to grow with bends and kinks that can cause short circuits. So, Mitra and his colleagues built a NAND gate that was immune to the effects of “bendy” CNTs. Based on the NAND gate and with the aid of simulators they designed, they developed an algorithm to create other types of circuit elements, regardless of misalignments.

CNTs were fed into a grid. If a tube appeared in an unwanted area of the grid, it was simply etched away or otherwise rendered useless. The group then could take things further by building algorithms that would work for entire circuit functions. The major remaining hurdle is finding a way to guarantee a given CNT will always make a connection.

See associated figure.

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