This demodulator is suitable for the quadrature phase-shift keying (QPSK) modulator previously published by the same author, *"Novel Low-Cost QPSK Modulator Needs No Adjustments" (*electronic design*, Sept. 16, 2002, p. 92)*. Also based on common CMOS logic, it requires no adjustments. These characteristics make it appropriate for low-cost applications, such as factory communications.

The typical approach to QPSK demodulation decomposes the modulated input signal via two multipliers driven by a fixed-frequency oscillator whose two outputs are 90° apart *(Fig. 1)*. This operation also produces terms at twice the rate of the oscillator. So, two low-pass filters (LPFs) are added to eliminate them. Finally, a parallel-to-serial converter translates the dibits to bits, thus producing the desired PCM signal.

An alternative demodulator that's suitable for the aforementioned QPSK modulator generates four modified carrier phases (0°, 90°, 180°, and 270°) obtained in the modulator by rotating the angles of the QPSK constellation. Then, a simple XNOR operation between each phase and the modulated signal will produce a logic "1" only if both coincide *(Fig. 2)*. If the received phase is 0° (related to dibit 00), all XNORs produce a logic "0." If the phase is 90° (dibit 10), only the upper branch gives a "1." This situation is inverted for 270° (dibit 01). In this case, the logic "1" is produced at the lower branch. But if the phase is 180° (dibit 11), a logic "1" is added to both branches. The result is the demodulated PCM signal.

In a practical circuit, the phase-references generator produces inputs to the XNOR gates *(Fig. 3)*. Also, the input, called ERROR (UART), adapts the initial phase reference in accordance with the circuit, *"Automatic Phase Detector For Digital Communications" (*electronic design*, Sept. 2, 1997, p. 168)*. This circuit forms a closed loop between the PCM signal and ERROR (UART) that provides the necessary synchronization for coherent detection. Like the modulator, this circuit runs for a carrier frequency of f_{m}/8. It has been tested at 2 MHz (with basic CMOS logic) and at 20 MHz (with HCMOS).