Signals with a know frequency but unknown phase may be detected using an in-phase and a 90° shifted reference signal, as frequently used in lock-in amplifiers, synchronous detectors, and frequency-response analyzers. The 90°-shifted signal is called the quadrature signal. By multiplying the received signal with the reference signals, the low-pass filtered outputs will represent the real and imaginary components of the received signal. Once the two components are known, this complex number can be converted into amplitude and phase.
When used for frequency response analysis, the system is excited with a sine signal and the output of the system is demodulated using the two references. Neglecting harmonics, the multiplication can be performed using square-wave reference signals, which control amplifiers with a digitally controlled gain of either +1 or −1. The frequency must be swept over the range of interest.
Designing a swept-sine generator with quadrature output isn’t a trivial task, though. For low-frequency purposes, an undocumented feature of Maxim’s MAX038 oscillator chip makes this easy. The MAX038 is a sine, triangle, and square-wave generator whose frequency can be swept over 2 to 3 decades by a control current. By switching the frequency-determining capacitor, this range can be considerably extended.
The MAX038 has an OUT signal output and a SYNC logic level output (when powered by ±5 V). The SYNC output always has a 50% duty cycle, but the duty cycle of the output signal can be adjusted. For quadrature purposes, the output signal should be adjusted to 50% duty. The chip also contains a phase detector that can be used to generate the quadrature.
Figure 1 indicates the phase relations of SYNC, OUT, and the phasedetector output (PDO). By setting a constant high or low level at the phase-detector input (PDI), one can select PDO to either lag or lead SYNC by 90°.
If PDI is connected to the SYNC output instead of a logic level, the frequency of the phase-detector output is twice that of SYNC. Also, the rising edge of PDO coincides with that of SYNC, which is the case for any duty cycle (Fig. 2).
The data sheet doesn’t give a detailed description of the phase detector and the circuit driving PDO—the output is simply described as a current source switching between 0 and 500 µA. This may be the case for its intended use, but not when loaded by a resistor to ground. When left open, the output alternates between about −2.3 and +4 V. The negative voltage apparently is an internal level with a source resistance of 10 to 15 kΩ. When loaded by 5 kΩ, the output swings between about −0.7 and +3.2 V. Being uncertain about the effects of loading on internal chip operation, a high-impedance load (i.e., a CMOS gate input) is recommended.
Ed-The following supplemental information about the MAX038 was provided by Roger M. Kenyon, senior member of the Applications Dept. technical staff at Maxim:
Mr. Olsen’s analysis of the relationships between the SYNC pin and the OUT pin is correct. In sinusoidal mode, the rising edge of SYNC corresponds to the rising zero-crossing of OUT. In square-wave mode, the rising edge of SYNC precedes the rising edge of OUT by 90°. Internally, the input signal received by the phase detector is a 90° lag phase-shifted SYNC signal (Fig. 3). Therefore, as demonstrated by Mr. Olsen, if the PDI pin is held high in sinusoidal mode, then a positive edge at PDO corresponds to a valley at OUT and a negative edge at PDO corresponds to a peak at OUT. If PDI is held low, then a positive edge at PDO corresponds to a peak at OUT and a negative edge at PDO corresponds to a valley at OUT. Because of this internal phase shift, the SYNC and PDO outputs are ideally suited for developing quadrature signals for OUT.
A typical application for the internal phase detector involves PLL operation. The signal applied to PDI is compared to the internal SYNC signal If the PDI signal has 50% duty cycle and is the exact frequency of the MAX038, the average output current of PDO is 250 µA (the output current range for PDO is from 0 to 500 µA). This current generates a voltage across a “gain” resistor (RPD) and an RC compensation network. This voltage is applied to the FADJ pin controlling the frequency of the MAX038 output. If the signal applied to PDI varies in frequency, the duty cycle of the PDO output changes and the average voltage applied at FADJ changes. This change in voltage changes the output frequency of the MAX038 to match the frequency applied at PDI. The value of RPD determines the range of the applied PDI signal so that the MAX038 remains “locked.” The maximum value of RPD is around 4.7 kΩ. Values above this will overdrive the FADJ input.