As designers strive to achieve true 3D IC packaging with through-silicon vias (TSVs), they have had some mixed results. First, there’s the good news. The implementation of TSVs is gaining momentum and garnering greater favor in the semiconductor industry.
There is the realization that semiconductor processing must gravitate toward smaller and smaller geometries in 3D formats from the present 2D formats, down from 45, 22, and 18 nm to even tinier dimensions to meet future market needs. And to that end, there have been shining examples of the advances possible in 3D packaging using TSVs for higher levels of integration.
Improvements in 3D stacking continue mostly for memory and logic functions as well as for certain types of chips like image sensors, III-V devices, microelectromechanical systems (MEMS) devices, and to some degree power devices. Witness the recent 8-Gbyte registered dual-inline memory module (RDIMM) from Samsung Electronics. It employs TSV die stacking that saves 40% of the power consumption of conventional RDIMMs, Samsung says. Many companies are ramping up their efforts to manufacture wide-I/O DRAMs that use silicon TSVs.
Now for the sobering news. The technology is not quite there yet and lacks maturity, despite its notable achievements. One major issue lies in determining who produces the TSV. Is it the fab facility, the etching or bonding facility, the packaging house, or someone else?
The industry is grappling with these choices, proposing three different processing options: putting the via at the front end of the line (FEOL), putting it in the middle of the process, or putting it at the back end of the line (BEOL). Most 3D TSV processes use the via in the middle approach and are close to being fully ready, but they still require more improvements in production throughputs to reduce costs further.
Current wire-bonding approaches for chip stacking have made notable advances. But most semiconductor IC experts agree that when you need high performance and wide bandwidths from devices like the latest microprocessor that entail hundreds of leads within an even smaller and more confined chip area, wire bonding won’t cut it. It becomes imperative to go to the 3D TSV route.
“The greatest challenge is the lack of standards, specifications, and a clear business model for implementing this technology across the entire supply chain,” notes Larry Smith, a member of the technical staff at Sematech, an international consortium of semiconductor manufacturers. “There are also technical challenges. Based on an industry survey we conducted last September, these include reliability, a lack of consensus on how to perform temporary bonding and de-bonding to drive down costs, designing for stress management to ensure that device characteristics are not shifted by proximity to TSVs, and chip-package interactions and stresses that adversely affect reliability.”
Furthermore, Smith points out that “3D stacking can solve reliability problems associated with die using low-k dielectrics. Bonding these die to silicon interposers or other silicon die that have the same thermal coefficient of expansion, instead of bonding them to substrates, will greatly reduce the cracking of these materials.”
Sematech, the Semiconductor Industry Association (SIA), and the Semiconductor Research Council (SRC) have announced a program to drive industry standardization and the technical specifications for heterogeneous 3D IC integration. Sematech is active in collaborative research for the semiconductor industry.
Semi International has also formed a standards committee that is calling for task force volunteers to explore, evaluate, and create consensus-based applications, guidelines, and practices for manufacturing stacked 3D ICs. Semi is a global industry association serving the supply chains for the microelectronics, display, and photovoltaic industries and works closely with Sematech.
As IC geometries shrink, chip dimensions and interconnects also shrink further, as do power requirements. Thermal management, signal integrity, noise, and cost-effective testing become huge problems. Thinner wafer carriers become more difficult to handle. Lower yields due to fewer known-good die (KGD) increase the cost of manufacturing per chip.
The bottom line is cost. Many processing experts believe that the semiconductor industry does not have an adequate cost model to evaluate the cost-effectiveness of 3D IC packaging using TSVs.
“The cost of ownership for TSV 3D interconnects is definitely higher than existing wire-bonding or flip-chip methods and should be less than $100/wafer,” says Steven Dwyer, vice president and general manager of the EV Group, North America. “However, if you look at the cost of ownership numbers based on functions/dimension (area or volume) and on the additional necessary investment for smaller-size nodes in 3D TSV interconnects, then the use of TSV integration looks more compelling.”
According to Anton Domic, senior vice president and general manager of the Implementation Group for Synopsys Inc., the cost overhead for a TSV-based 3D chip is $150 per wafer, which represents only about 5% of the total cost of producing a 300-mm wafer. However, other experts say this figure represents the cost of only drilling the TSV in a chip and does not include processing, packaging, and other costs.
“We’re just seeing the tip of the iceberg in true 3D implementations using TSVs,” says Dan Waller, director of advanced packaging for Brewer Science. “The semiconductor industry is not going to be able to achieve the segmentation needed to separate RF, power, discrete, MEMS, and other devices, as it scales down to smaller geometries. The relative costs of 3D TSVs may seem high, but the benefits are important and will be driven by the design houses like the Apples, Qualcomms, etc.”
“We’ve done some calculations that show that TSVs will take up only about 5% of a die’s space, versus 10% for wire bonding,” adds Mark Previtt, Brewer Sciences applications engineering manager.
Brewer Science has been in the high-integration level of 3D IC packaging materials for about five years, specifically for thin wafer handling. It’s one of the original packaging materials companies, starting with a partnership with EV Group. It is focused on process developments in connecting materials and processing equipment and has developed the ZoneBond method for TSV implementation.
“3D TSV wafer bonding/de-bonding manufacturing capability is already available and is in use in more than 50% of process flows,” says Wilfried Bair, Suss Microtec’s general manager. “A fab facility may start out with low yields using 3D TSVs, but they can optimize via diameters and aspect ratios to improve those yields as they go along in the process.”
“We have the capability to provide TSVs on CMOS. We’ve been doing it for quite some time with MEMS and gallium arsenide (GaAs) using deep reactive ion etching (DRIE). Many DRIE equipment and wafer bonders can enter the 3D TSV market since these are two pieces of equipment CMOS houses normally do not have,” says Paul Werbaneth, vice president of Tegal Corp.
“Many fab facilities are reticent to invest money and time into getting RIE equipment, which they’ll need as IC geometries scale down further. For high-volume manufacturing of ICs with silicon TSVs, they’ll need reliable wafer-handling equipment for various substrates, high silicon etching rates with high-quality side wall profiles, and robust silicon DRIE processing,” Werbaneth says.
Further, Werbaneth also cautions that DRIE is a plasma etching process as used in MEMS and that it must be optimized for use on silicon for 3D TSVs since it can cause some damage to the wafer if not enough attention is paid to it.
Cost-effective solutions of 3D ICs have been shown for wafer-level packaging (WLP) and chip-scale packaging (CSP) using 6-in. wafers. Memory stacks integrated with logic elements using 3D interposer caps have been shown to be cost-effective on 8-in. wafers. And, package-on-package (PoP) and system-in-package (SiP) solutions are keeping pace with the market need for dense 3D ICs. But as package heights shrink, that cost will lead to the implementation of true 3D stacking using TSVs (Fig. 1).
The embedded wafer-level ball-grid array (eWLB) has been developed to extend the package’s size beyond the area of the chip. This fan-out wafer-level package (FO-WLP) enables 3D applications such as SiP on wafer as well as discrete component embedding using TSVs. STATS ChipPAC, STMicroelectronics, and Infineon Technologies have shown applications for a double-sided eWLB package in a PoP, as well as a SiP approach (Fig. 2).
Interposers Ease The Way
Chip stacking using silicon and glass interposers is the latest approach for denser 3D ICs. Known as 2.5D integration, it will ultimately lead to true heterogeneous 3D ICs that allow the mixing of processor, logic, memory, power, discrete, RF, MEMS, and other components. In fact, the use of silicon interposers is more prevalent than the use of glass.
“The main application area presently driving interposer development is high-performance computing,” believes Eric Beyne, science director at the advanced packaging and interconnect research center of Belgium IMEC.
“Glass interposers are at least a decade away, but they will have a major impact in cost savings once they emerge on a large scale,” adds Previtt of Brewster Sciences.
Singapore-based NEPES Ltd. recently unveiled a silicon interposer module that’s less than 0.8 mm thick and includes two 7.0- by 7.0-mm bumped die. It also contains both integrated passive devices and 65-µm diameter TSVs. The module’s 0.2-mm thick interposer has copper TSVs and a multiple redistribution layer (RDL) on both sides. Its low band-pass filter consists of thin-film metal-insulator-metal (MIM) capacitors and spiral inductors. The BGA balls and the TSVs are manufactured on 0.4-mm pitches.
Prototypes of high-performance and advanced 3D ICs using interposers may appear this year. Semtech is working with IBM, using IBM’s 3D TSV technology, to develop a high-performance platform consisting of analog-to-digital converters (ADCs) and DSPs. The platform will use IBM’s interposer technology to interconnect ADC functions in IBM’s custom logic SOI-based (silicon-on-insulator) Cu-45HP technology with interleaver ICs in IBM’s 8HP biCMOS silicon-germanium (SiGe) technology.
Dorota Temple, senior fellow at RTI International, points out that 3D silicon interposers can be used for stacking memory, FPGA, sensor, and ASIC devices using back-side multilevel metallization and copper-filled (or unfilled) vias and front-side multilevel metallization using copper dual damascene or spin-on dielectrics like benzocyclobutene (BCB) or polyisoprene (PI) materials (Fig. 3). RTI is the second largest non-profit institute in the U.S. and is pursuing multi-disciplinary research into advanced technologies like 3D IC interconnects.
Xilinx has taken a major step in 3D TSV technology with a stacked silicon interconnect that creates multi-die FPGAs that use silicon interposers for wide bandwidth and high packaging density. Based on an innovative interposer design, it enables a die-to-die bandwidth improvement of 100 times per watt and a twofold to threefold capacity advantage over monolithic devices. The IC package is part of Xilinx’s 7 series FPGAs made on a 28-nm process.
One entrepreneur, Zvi Or-Bach, is proposing a novel approach using anti-fuse technology to stack FPGAs in a 3D format without needing TSVs. His company, NuPGA Corp., has provided details of this approach, which he says yields densities comparable to those of ASICs. It achieves these densities by moving the high-voltage transistors needed for anti-fuse programming underneath the 3D structure (Fig. 4).
Lest it be forgotten, the direct-bond interconnect (DBI) technology from Ziptronix has been around for quite some time and has been successfully used for integrating imaging sensors onto CMOS substrates. According to the company, it’s the lowest-cost 3D process using TSVs. Unlike other 3D processes, “it is the only option to perform 1-µm and 2-µm pitches without affecting process yields,” explains Chris Sanders, director of Ziptronix’s business development.
“The benefits of our DBI process do not decrease with decreasing line geometries,” adds Paul Enquist, Ziptonix’s chief technology officer and vice president of R&D. “We continue to refine our process to accommodate future microprocessor and mixed-signal applications.”
The CMOS BEOL process employs an optimal solution for large-scale, profitable 3D IC integration with high yields and high throughput. It involves direct oxide bonding technology that incorporates conductive or metal-to-metal bonding while eliminating the high temperature and pressure required for conventional copper-to-copper thermo-compression bonding processes (Fig. 5). It can be used for die-to-wafer and wafer-to-wafer stacking.
Software And Testing Are Leading Issues
Software will play a major role in 3D TSV developments. Thermal and simulation modeling and analysis will become mandatory tools for designing 3D TSV structures, as will be the use of EDA tools for floor planning in the early phases of a TSV-based 3D chip’s design. Anton Domic of Synopsys points out that the road from 2D to 3D must be carefully paved to be technically and economically viable for all the players, including EDA companies, and it will require a true collaborative effort from all sides.
Testing is certain to pose a tremendous challenge for TSV-based 3D ICs. Bill Bottoms, chairman and CEO of Third Millennium Test Solutions (3MTS), sees problems in being able to reliably determine on and off logic states, given the fact that future high-density devices will be operating at very low voltages to keep power dissipation levels low.
“Working at a theoretical requirement of three test vectors per transistor for 100% fault testing coverage, we’re going to be looking at close to a trillion IC vectors needed, and that will not be cost effective to do,” he explains. “Testing for KGD will be very hard to prove. One common test need for TSV-based 3D ICs is for lowering the cost of probing fine-pitch microbumps.”
One way to tackle this problem is to incorporate more self-testing features on the chip. Sematech’s Smith expects different companies to develop their own proprietary test architectures that will be company-specific and application-specific.
There is a large effort in standards activity to extend JTAG to 3D stacks. To that end, the IEEE held its first 3D test workshop in conjunction with the international Test Conference (ITC), Nov. 4-5, in Austin, Texas. During the conference, Tezzaron Semiconductor CEO Bob Patti explained how his company’s proprietary solution, Bi-STAR (built-in test and repair), can be helpful for testing DRAM 3D stacks.
Patti says that Bi-STAR performs a greater level of testing than what is available during normal chip or wafer-level testing, explaining that it can repair bad memory cells, bad line drivers, bad sense amplifiers, and shorted word and bit lines. It can also repair leaky bits, bad secondary bus drivers, and bad content-addressable memories (CAMs).
Brion Keller, senior architect at Cadence Design Systems, emphasizes the need for new testing methodologies for 3D IC design and test that include integration between design for test /automatic test-pattern generation (DFT/ATPG) diagnostics.
A Look Ahead
Although some semiconductor IC manufacturers are predicting cost breakthroughs soon, most experts on 3D IC packaging believe they won’t happen for at least two more years. These experts point out that there is no infrastructure available for high-volume manufacturing of large-size wafers or panels and that it will take of a couple more years for one to be realized. But they also caution that the potential benefits of TSV-based 3D ICs can be achieved with even larger wafers, such as 12-in. wafers.
3D IC integration leading to ultra-compact microsystems—with integration levels that are denser by an order of magnitude or more than present levels—is sure to inspire a new world of application possibilities. However, reducing an IC footprint’s volume by 3D stacking will only make sense if other supporting components such as batteries, antennas, passive components, and sensors are proportionally reduced as well.
The author would like to thank the organizers of the 3-D Architectures for Semiconductor Integration and Packaging (ASIP), Technology Venture (http://techventure.rti.org), held Dec. 8-10, 2010, who provided valuable last-minute conference proceedings. He is also grateful for the help provided by Roger Grace of Roger Grace Associates in reporting on this conference and in providing key insights into 3D IC packaging technology (www.rgrace.com).
Readers may wish to learn more about system-level integration by attending the upcoming Smart Systems Integration 2011 Conference and Exhibition, March 22-23, Dresden, Germany, sponsored by the European Technology Platform on Smart Systems integration (EPoSS). Go to www.messago.de/en/SSI/main.htm.