Recently a guy asked me to present a lecture to the Silicon Valley ESD Society—a lecture about ElectroStatic Discharge. That's a little like bringing coals to Newcastle—what the heck could I tell them that they did not already know? I did know how I would start out. But after the beginning, then what? And if I wrote down everything I told them, would that make a useful, valuable column? Let's see...
First I told them about the ESD newsletter we started at National a few years ago. The purpose was to inform all of the engineers of new developments so we could meet high levels of ESD on our new ICs with a minimum amount of wasted effort. Jolly good. Shortly after that, the editors posted a list of the ICs that would survive a very high ESD rating. We were exhorted to go out and learn how these engineers got such good ESD ratings. Two of the best three were digital ICs, so all of our analog engineers were encouraged to learn the secrets of that one "robust" analog circuit that would pass not just 2 kV, or 4, but 6 kV of ESD. Hey, that's really a very good, strong ESD circuit. How did those designers do it? With a special ESD protection algorithm and special clamp diodes? Let's find out what this circuit looks like!
First, what's the name of this IC? It's an LM340. Okay—do you guys recognize the part number? The LM340 is a 1-A, 3-terminal regulator, and for all intents and practical purposes, it passes a high ESD test by the brilliant strategy of having a 1-A power transistor on every pin. So, if we want to design a quad op amp with really good ESD ratings, obviously all we have to do is add twelve 1-A power transistors, one on each input and output pin. Of course, the die size of an LM324 would increase by a factor of 9, and the input capacitance and leakage would be completely unacceptable. Everybody would love the ESD ratings, but nobody could afford the circuit. In fact, we could not even fit it into a 14-pin DIP package. But if we're to learn from the LM340's designer (George Cleveland) and if we applied his teaching so as to achieve the highest ESD ratings, then that's the circuit we would design. Ahem. Ahem! Needless to say, we came up with some slightly more compact and cost-effective circuits to protect our new ICs.
Similarly, one of our customers wanted to see our report on ESD on a new IC. It passed the required 2-kV test on 37 of the 40 pins. So the customer proposed that we must add a new ESD cell to all of the pins to improve the ESD ratings. After all, the customer wanted the highest possible ratings. But we observed that if we add the ESD cell to every pin, the die size would increase by 12%, the yield would drop, and the cost per IC would increase by several percentage points. If they wanted to have the highest ESD tolerance, did they want to pay for it? No. So, after much debate, they decided to accept the part with the ESD cell added to only those pins that needed it. That was what they were willing to pay for.
Now, most people have an adequate awareness of ESD problems. If you walk across a carpet on a dry day in winter and bring your finger near a circuit, it's real easy to generate a spark that might damage the circuit. The industry has a reasonably accurate model of this abuse: Charge up a 100-pF capacitor to a couple thousand volts, and then discharge the capacitor through a 1500-Ω resistor into a pin or node of a circuit. This impedance is commonly known as the "human body model." This is considered a fairly minimal ESD test, yet it puts a surge of 1.3 A through most paths for a couple hundred nanoseconds. That's pretty scary for a little IC where the data sheet tells you to never exceed 10 mA into any pin. A lot of good ICs will pass this test, and even if the voltage is doubled, (note also that the energy will quadruple) some ICs survive just fine. But a lot of them do not. So if you are building a million radios, there's a definite incentive to buy semiconductors that are pretty reliable. Minor accidents that cause an occasional zap to a circuit may occur even though every assembler or worker on the production line is carefully grounded through a 1-Ω wrist strap.
Now, when is a piece of "grounded" test equipment not "grounded?" When you can measure 500 V on some parts of the equipment, for example. (Once I saw a lab where two workbenches, about 7 feet apart, had 2500-V ac between them...a long time ago.) When is a 1-MΩ floor not 1 M\[ohm\]? When the janitor decided to wax it... What is the main difference between a conveyor belt on a production line, and one on a Van de Graaff generator? Answer, one is vertical and the other is horizontal. But both can generate lots of volts.
So, to make sure our ICs are reliable, we have bought various ESD testers, and we perform all sorts of zap tests on our new and old ICs. I once wanted to add a Zener diode to a pin of one of my ICs to prevent damage to a differential pair. One of the senior engineers said, when he saw my drawing, "You'll get in trouble when that Zener gets zapped by ESD." But after a lot of thought, I left it in anyway, and in actuality, we have never had any customer complaints about that terminal. I checked recently, and that IC has passed 2000 V on every pin—even the pin with the Zener. So when an expert tells you, "You have to do this, and you can't do that," just remember that even experts can be wrong...
One major purchaser of ICs came out with a drawing for the "Machine Model" of ESD testing. This represents what happens when a device is held in a large metal arm, inadvertently charged to a high voltage, and then it touches a grounded piece of metal. In this test, a 100-pF capacitor is discharged through 0Ω (not 1500 Ω) into a device's pin. Well, if you could really discharge a capacitor through 0 Ω, the current would be infinite, right? Ah, but there's always some inductance. And if you stand at the DUT and look back at the capacitance, the wiring has a certain characteristic impedance or resistance—perhaps 50 Ω, perhaps 90 Ω. That helps explain why you can't have an infinite current, and you can't have 0 Ω. After several suppliers complained to the Customer that it wasn't realistic to have a source impedance of 0 Ω for that test, the Customer changed the control drawing to say "0 Ω ±5%." Still, despite cases as silly as that, it's important when you do your ESD testing to keep your wires fairly short and compact, to keep the inductance low. This gives a fair rise time for the current pulse. No point in trying to fool everybody, including yourself, with a wiring path that causes slow rise times.
National bought a $200,000 Zap-Master ESD tester from Keytek*—there are only two in the world (AT&T has the other one). When we test parts and get results, they don't agree with AT&T's results. That's because AT&T chose to use their machine to apply pulses, both + and -, into a grounded part. NSC chose to apply a high voltage bias to the DUT and discharge the part into ground, which is a more severe test. It just goes to show that there are many disagreements on what is the "right" way to do an ESD test. There isn't necessarily any fully-agreed-upon procedure, no "industry standard," no repeatable test, no consistent results. However, we've been able to use some of these tests to design ESD structures that not only meet good ESD ratings, but are also predictable by Spice analysis. So if Spice can teach us what is good, maybe it can teach us what is better. If we are able to come out with consistently improved stress ratings in a year or two, I will be impressed, and amazed!!
What happens when one IC of a lot of 30 fails at 1300 V, and the other 29 survive past 2300 V? That's very frustrating, and it may indicate a minor manufacturing flaw (a pin-hole oxide flaw?) that happens at a low occurrence rate. Sometimes you get 11 out of 30 failing at 1300 V and 19 good at 2300 V. Very confusing. One guy pointed out that this can happen when some of the gates and flip-flops start up in one output state, which is more resistant to stress. If the gates bias up to the opposite state on another pulse, the part might fail. So, sometimes you can test a part five times at 1600 V and it's okay, yet the next test at 1200 V causes a failure. Does it sound to you like there's something nonlinear going on??!! Well, if you think it's fun to analyze circuits in Spice at audio frequencies, just imagine how much fun it is to analyze the transient response of a little piece of an IC, where the current builds up to a couple amperes in 10 ns! Some engineers, though, seem to be making some progress in this area.
But what if you test a batch of ICs and they're all passing 2400 V just fine, yet you take them over to another tester and they start failing at 1400 V? Does that mean that the first half of the batch of ICs is much stronger than the second half? No, that's not the case. That dichotomy usually occurs because the second ESD tester—the one that belongs to the Reliability Group—is well calibrated. The problem arises because the first tester, which is kept around the development engineering lab, has gone out of calibration and is putting out MUCH too low a pulse. Thus, the parts are made to look good due to false testing. Let me assure you, I've heard of this happening several times. In fact, a guy told me yesterday that it happened again to his newest IC. His initial test led him to think it was okay, but the accurate tester told him that it really was not. We were fooled, but not for long.
I told him to go out and make up a calibrator network to add onto the ESD tester. The network is really very simple, as shown in Figure 1. The exact R and C values aren't important, but you really do want to understand the philosophy. Every time you "hit the button" to discharge the capacitor, a certain quantity of charge (Q = C ⊗ V) is dumped down into the big capacitors. If the total capacitance is about 1 µF, then 200-mV output change corresponds to 2 kV of ESD pulse. So the main thing is to have C2 at about 1.0 µF. I like to make C2 out of a couple selected 0.47 µF caps. Why selected? Well, if the first two capacitors I grabbed were 0.52 µF, the calibration factor would be off, and it would be hard to trim to get the right scale factor. So the selection process is to select 2 or 3 capacitors that make up 0.95 to 0.99 µF total. Then add on some trim caps to get the total near 0.997 µF. That covers the calibration.
Why bother to have C1? Well, if you force a 2-A pulse into a wound film capacitor, the inductance of the windings might cause a voltage overstress of the film. It's better to have C1 = 3000 pF so that the pulse of current fed to C2 doesn't have any extreme values. The other good thing about C1 is making it out of three 1000-pF capacitors, perhaps NP0 ceramic or silvered mica, that are standing up like a tripod. Then, if you make C2 out of two film capacitors that act like a bipod, the whole scheme stands up off a little piece of copper-clad fairly strong and rigid, not wobbly as it would be if you just used one capacitor for C1 and one for C2.
What about R1? Well, I would use 47 k or 47Ω, carbon composition, Allen Bradley 1/2 watt. The resistance value is not a big deal, but you really should use a carbon-composition type that can handle an ampere or two without breaking down (if you used a film resistor, the high di/dt of the pulse is likely to cause a momentary break-down between adjacent spirals). A good value for R2 would be 47 k or 100 k, also AB 1/2-watt carbon composition. Because this resistor is unlikely to see more than 300 V, it's not so critical, but I like to use carbon comp to remind me that film resistors aren't always preferable.
If you have a voltmeter with an Rin of 10 MΩ, that's not quite as good as 1000 M&)mega;. But you will be able to see an indication that a 2-kV pulse does give something like a 200-m V jump. Heck, 180 is substantially the same as 200. But an indication of 160 or 130 m V would be wrong. This isn't necessarily a precision calibrator, but it's a pretty good lie detector. After all, it works on the conservation of charge (not the conservation of energy). The note we are putting on our ESD testers and calibrators says:
"1. Do not remove this calibrator under pain of death.
2. Many of these ESD testers have been known to fail in a mode with an actual pulse output amplitude of 1/2 to 1/4 of the indicated voltage.
3. Therefore, every day you use the tester, check its calibration. Set the pulse level to 2000 V and watch the output jump 200 m V for each pulse. If 4000 V, expect to see 400 m V. You can short the 1 \[my symbol\]F to ground to reset it, or, just put your fingers across it.**
4. Calibration procedure is available from Cal Lab, Paragraph 93-14. (Measure total capacitance = 1.0 µF ±1% when R2 is shorted out.)"
Anyhow, for the last 6 months I knew that I would eventually write a column on ESD, but I didn't have any strong motivation or impetus to do it. Nothing really important to say. But as soon as I recognized the importance of having a simple calibrator to help you catch your ESD tester as soon as it goofs up, that drove me to draft up and finish this column, pronto—and here you are.
All for now./Comments invited! RAP/Robert A. Pease/Engineer
Address: Mail Stop D2597A (note change!), National Semiconductor, P.O. Box 58090, Santa Clara, CA 95052-8090
*Keytek Corp, 260 Fordham Rd., Wilmington MA 01887.
** One of our legally oriented guys suggested a disclaimer: Whenever he hears the world "kilovolt," he doesn't want to go around touching anything, even if the DVM says 0.42 V... So, okay, go ahead and rig a push-button switch to short out the 1 æF, if you want to. BUT, a 4-k V pulse from a standard human-body-model tester doesn't BITE or TICKLE much at all. It sure doesn't hurt most people....