Methodologies to Mitigate Chip-Package Interaction (.PDF Download)

Aug. 5, 2015

In high-performance semiconductors, the back-end-of-line (BEOL) interconnect pitch has been shrinking for decades following Moore’s law. Steady advances in very-large-scale integration (VLSI) technology for both digital and analog devices could never have been achieved without overcoming various reliability risks in IC chips as well as packages...

Register or Sign in below to download the full article in .PDF format, including high resolution graphics and schematics when applicable.

Sponsored Recommendations

What are the Important Considerations when Assessing Cobot Safety?

April 16, 2024
A review of the requirements of ISO/TS 15066 and how they fit in with ISO 10218-1 and 10218-2 a consideration the complexities of collaboration.

Wire & Cable Cutting Digi-Spool® Service

April 16, 2024
Explore DigiKey’s Digi-Spool® professional cutting service for efficient and precise wire and cable management. Custom-cut to your exact specifications for a variety of cable ...

DigiKey Factory Tomorrow Season 3: Sustainable Manufacturing

April 16, 2024
Industry 4.0 is helping manufacturers develop and integrate technologies such as AI, edge computing and connectivity for the factories of tomorrow. Learn more at DigiKey today...

Connectivity – The Backbone of Sustainable Automation

April 16, 2024
Advanced interfaces for signals, data, and electrical power are essential. They help save resources and costs when networking production equipment.