Electronic Design

Chips In Space: On-The-Fly Intelligence

Conventional wisdom has it that the consumer market will drive the next stage of growth in electronics. But designers should also be aware of investments in the military command, control, communications, computer, intelligence, surveillance, and reconnaissance (C4ISR) infrastructure. It isn't necessary to be a defense contractor to participate. It may not even be necessary to have military systems as a target application.

Case in point: Over the past two-and-a-half years, Honeywell Aerospace and Cypress Semiconductor engaged in a joint project to upgrade Honeywell's existing 350-nm radiation-hardened silicon-on-insulator (SOI) technology to the 150-nm generation, based on Cypress' experience with 180- and 130-nm bulk silicon. Synopsys joined the effort in the past year, adding its porting tools and design flow to the new process technology. The company also made its design centers available to ASIC engineers who are developing chips on the new process.

The effort is providing something different to each company. Honeywell, primarily a military contractor, gets accelerated development of a new rad-hard/rad-tolerant process technology for its defense customers. Cypress, essentially a merchant chipmaker, gains experience with SOI, which could potentially bring the one-transistor (1T) DRAM cell to scale below 100 nm (see "Scaling The 1T DRAM Cell," p. 52). Synopsys expands its customer base and attracts design center business.

Results from the three-company project are being monitored by the U.S. Department of Defense (DoD) for its new generation of military satellites. The satellites will use advanced custom chips that can pre-process raw information literally "on-the-fly" in orbit before passing it on (Fig. 1). The DoD is relying on a number of initiatives to create an IP-centric C4ISR system. Such a system will overcome the "stove-piping" of information that led to lapses in anticipating and dealing with the attacks of September 11, 2001. (To be fair, a number of these initiatives were set in motion well before that date.)

In mil-speak, stove-piping refers to information traveling up and down in an organization with little horizontal sharing between organizations. One recent example is the communication gap this June between the FAA and the U.S. North American Air Defense Command. The plane bearing Kentucky Governor Ernie Fletcher to President Reagan's funeral may have been seconds away from being shot out of the sky because while the FAA knew the plane had an inoperative transponder, NORAD did not.

The underlying concept is a sort of shared military/intelligence community version of the Internet, the Global Information Grid (GIG) (see "The GIG Is Up: A Guide To Netcentric Warfare Programs," p. 52). The GIG's backbone would be a network of satellites communicating with each other, with aircraft, and with earthbound users. It would constitute something more than a packet-switching backbone. To speed the dissemination of information, these satellites would pre-process intelligence and tactical data in space (Fig. 2) (see "A Netcentric Warfare Bibliography," DRILL DEEPER 8579). Accomplishing this, though, will require large and complex custom chips manufactured on advanced-geometry processes.

That's where the Honeywell/Cypress/Synopsys SOI effort comes in. CMOS built on SOI (Fig. 3) is subject to far fewer radiation-induced error sources and failure modes than CMOS devices fabricated on bulk silicon (see "It's A Jungle Up There: Radiation Effects In CMOS Devices," p. 54). Other approaches to radiation hardening exist, such as adding protective circuitry and error-correction software. But where gate density and throughput are critical, SOI permits the use of simpler circuits without error correction. SOI also yields about a 30% power advantage over bulk silicon and between 20% and 30% better performance. Additional circuitry makes the part not only rad-tolerant, but also rad-hard, improving performance and density even further. Honeywell's rad-hard 350-nm experience demonstrates between one-and-a-half to two times higher density with SOI than with a comparable-generation bulk-silicon technology.

Recognizing the advantages of SOI, the DoD established the Radiation Hardened Microelectronics Accelerated Technology Development Program in July 2001 to establish on-shore capability for 150-nm SOI. Honeywell is one of two contractors under this program.

Gary Kirchner, director of engineering at Honeywell's Defense & Space Electronic Systems Solid State Electronic Center, contrasts the then state-of-the-art 350-nm SOI process technology with what is under development: "Honeywell's 350-nm technology had an ASIC capability up to 1.5 million usable gates with five metal layers. It ran on a 6-in. line at our Plymouth, Minn. facility. The 150-nanometer technology that we're co-developing with Cypress is capable of 10 million usable gates, has six metal layers, and runs on 8-in. wafers at Cypress' Bloomington, Minn. fab. When we port it back to our Plymouth facility, we'll also be bringing up an 8-in. line."

As of July, Honeywell has "the capability to do the full front end of the line, that is, creating the transistors up to the contact," Kirchner says. "That is being followed by a phase-two upgrade so we can do the full back-end metal. By the end of 2004, Cypress will be in full production, and by the end of 2005 or early 2006, we'll have transferred the technology to our fab."

Because they don't possess extra circuit-level hardening, Cypress' rad-tolerant ICs will spec lower total-dose hardness capability than Honeywell's rad-hard parts. But, Kirchner explains, rad-tolerant and rad-hard will be design-rule compatible, and the models and electrical performance will be identical between the technology at Cypress and the technology once it's moved to Honeywell. The same designs will be able to run in either facility.

Like Cypress, Honeywell is excited about 1T DRAM, and not just because of its smaller cell size. It also uses very low power and can efficiently refresh the entire memory array all at once, with relatively long periods between refresh.

However, Honeywell has also been working with Motorola on magnetoresistive random access memory (MRAM) as a totally rad-hard nonvolatile memory component. MRAM is unlike either flash or E-squared memories, which are sensitive to total ionizing radiation and need extra shielding and error correction. Honeywell will create the rad-hard transistor underlayers and place Motorola rad-hard MRAM bits on top.

With the Synopsys partnership, Honeywell was looking for a way to reduce the risk of creating really large ASICs. Because its experience had been limited to the 1- to 1.5-Mgate level, Honeywell engineers felt that the company required a major leap to get up to the 10-Mgate level. Kirchner explained that Synopsys had not only the tools and the flow, but also a design services group that had already built a number of 15-Mgate commercial ASICs.

"Synopsys also has an umbrella over its tool flow that allows collaboration across multiple design sites at different geographical locations," says Kirchner. One of Honeywell's existing customers is already porting a previous design to the 150-nm technology using the Synopsys flow and collaborative environment.

At this point, Honeywell is following the Cypress life cycle by going through all of the normal gates Cypress process engineers would go through when bringing up a new technology. As of mid-July, says Kirchner, Honeywell and Cypress were no more than two or three months away from the production-upgrade gate. He notes that the SOI technology exhibits the same defect density and yields as Cypress' commercial bulk technology, yielding "very well" on half-million gate designs that have run through the process, as well as on a 5-Mbit SRAM.

Chris Seame, Cypress' executive vice president of technology and manufacturing, says that when Honeywell came forward, Cypress had not made any decisions about SOI but had been looking into the technology for several reasons. Among them are its potential for alleviating problems with power/speed tradeoffs for high-performance parts, its promise to ameliorate some of the soft-error problems prevailing throughout the industry, and the ability of SOI 1T DRAM cells to eliminate the scaling problem of the capacitor in 1T-1C DRAM.

"For us," he says, "it was a fairly low-cost way of getting into SOI and trying out some of our circuits and seeing what we could see. We've now learned that SOI works and that we can make it in our factories with only slight modifications to our baseline technology." He adds that Cypress already had an MRAM effort of its own under way, and he expects that something will come of that in the near future.

Well before September 11, 2001, the U.S. military had plans for using Internet Protocol as the common element in a web of C4ISR systems. As such, it would make more data available more quickly, and in a usable form, to intelligence services, battlefield commanders, and tactical units.

Of course, the attacks of September 11 highlighted the need for up-to-date intelligence sharing. In mil-speak, stove-piping was a major failure mode.

Government investment in new programs to push clear, useful information to those who need it most is expanding. For example, in January 2004, DoD awarded a total of $944 million in contracts to Lockheed and Boeing to develop the next generation of satellites for the U.S. military. The two companies will compete for a $6 billion development and hardware contract to be awarded in 2006.

While Lockheed and Boeing are traditional military contractors, the government isn't limiting participation to that side of the economy. The military recognizes that while the Internet may have evolved from ARPANET, in today's world the commercial sector is the principal source of ongoing innovation.

However, the government isn't limiting participation to that side of the economy. In an article in Intercom, The Journal of the Air Force C4 Community, Lt. Gen. Tom Hobbins, deputy chief of staff for warfighting integration, speaking of the Air Force-led Transformational Satellite program, says that "two years of architecture-based studies cast the TSAT from the outset as a component of a joint, interagency network architecture. Potential technical approaches balanced industry and commercial solutions with more specialized capability." \[Emphasis added.\]

Invitations to participate are on the table. According to a National Security Agency Web site, "Achieving \[this\] vision requires substantial augmentation of today's information-sharing technology features and new technology capabilities. The preponderance of GIG functionality will be realized through leveraging commercial technologies and standards, augmented as necessary to meet unique DoD mission-critical needs for availability, integrity, confidentiality, access control, and non-repudiation.

"Products available today will not satisfy many of the capabilities needed to support IA in the net-centric GIG vision. With an emphasis on commercial solutions for the GIG, a coordinated interface with commercial, contractor and government development communities is essential. A spiral/evolutionary approach to development over the next several years will deliver incremental improvements as new technologies become available." \[Emphasis again added.\]

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