Electronic Design
Design Tool Streamlines SoC FPGA Application Creation

Design Tool Streamlines SoC FPGA Application Creation

Xilinx’s SDSoC represents a major shift in support for SoC FPGAs. It opens FPGA development to software developers without requiring a major investment in time and effort to utilize the hardware design tools.

Xilinx’s original Zynq-7000 included a 32-bit, dual-core ARM Cortex-A9 with its FPGA (see “FPGA Packs in Dual-Cortex-A9 Micro”). The latest Zynq MPSoC pushes the envelope with a 64-bit, quad-core, Cortex-A53 plus a dual Cortex-R5 (see “16-nm FPGA Includes 64-bit and Lockstep ARM Cortex Cores”). They can greatly simplify FPGA designs by incorporating a system-on-chip with the FPGA fabric providing an efficient programming platform that can be easily melded with logic implemented by the fabric.

In the past, hardware designers would develop the FPGA logic that could then be accessible by the software created by programmers that would run on the SoC’s CPUs. Converting parts of an application so they would reside in the FPGA fabric was next to impossible for most programmers and a challenge for many hardware designers. The task is more than just designing the logic necessary to implement a logical “black box.” There is also the hardware and software interface support.

Xilinx’s Vivado FPGA integrated development environment (IDE) has made the task of creating designs that support the SoCs much easier (see “FPGA Design Suite Generates Global Minimum Layout”). Still, it required a hardware and software designer to collaborate, regardless of the complexity of the system.

Xilinx’s new SDSoC builds on Vivado, but adds the ability to designate a portion of C/C++ code to be moved to the FPGA fabric instead of being implemented in software (Fig. 1). SDSoC handles the translation C/C++ to HDL generating the corresponding FPGA interface as well as providing the software interface to the logic moved to the FPGA fabric.

1. Xilinx’s SDSoC allows software developers to select code to be converted and moved to the FPGA. It also provides the profiling tools to test these changes.

The desire is to offload the CPU and utilize the FPGA’s inherent parallelism to provide a major performance boost to the application. Of course, some translations will prove more efficient than others because it is possible to use this approach and wind up with a system that runs slower than software alone. This is regardless of whether the translation is done by SDSoC software or a person. This is why the inclusion of profiling support is so important (Fig. 2).

2. SDSoC’s profiler provides feedback on how efficient the programmable logic is compared to its software-only counterpart.

The system-level profile provides software/hardware cycle accurate performance and hardware utilization information. The system provides automatic creation and instrumentation of cache, memory, and bus utilization using the AXI-Performance Monitor (APM). This allows exploration of different interconnect and memory interfaces.

Using the system from the IDE is a matter of selecting the functions that will be migrated to hardware. The profiling provides rapid area and performance estimation. The optimizing compilers can convert serial programs into parallel implementations. Different data import/export models can be used, such as DMA scatter-gather.

SDSoC supports software that runs on operating systems like Linux and FreeRTOS as well as bare-metal software applications. The software support is an extension of the Xilinx SDK that runs on the Eclipse IDE.

Software debugging works as usual until code is moved into the FGPA, at which point the interfaces can have breakpoints but similar access to the FGPA logic is not possible. Breakpoints can still be used when in “estimation” mode. This is essentially the midpoint between full software implementation and full hardware implementation of the function where the program is running within a simulation of the FPGA used to obtain profile data that a developer can evaluate.

Xilinx is also delivering libraries created using this approach. They have been optimized by Xilinx designers and the same approach can be used with third-party platforms. These include libraries like BLAS and OpenCV as well as DSP, video, fixed-point, and linear algebra libraries. These are C-callable libraries that can be used with a C application.

SDSoC can be used with existing Zynq development boards like the Zed Board and MicroZed (see “Hard-Core FGPA Provides a Flexible Development Target”). Market-specific platforms will be delivered for applications like video and software defined radio (SDR) that take advantage of migration of software libraries to the Zynq-based FPGAs.

The SDSoC software is not part of the free Xilinx IDE available with many Zynq boards, but the hardware designs created by SDSoC can be incorporated into any Vivado project. This means it is possible for a designer to migrate portions of an application to the FPGA fabric and provide this IP to others in the same fashion as a custom IP design done using the conventional FPGA design tools. SDSoC will be offered both as a standalone tool and bundled with the Vivado Design Suite System Edition.

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