Electronic Design
A Hands-On Tour of xCORE-200

A Hands-On Tour of xCORE-200

Technology Editor Bill Wong takes a hands-on look at XMOS' xCORE-200 development kit.

The xCORE architecture developed by XMOS is a bit different from most microcontrollers and microprocessors (Fig. 1). The xCORE-200 family features chips with up to 32 logical cores delivering over 4000 MIPS. With that many cores, designers can dedicate one or more to specific interface or compute chores. That speeds response time, because a core can wait for an event instead of polling or using interrupts.

A number of RTOS features are incorporated in the hardware, such as scheduling support. The architecture is well-suited for synchronous or time-sensitive applications like audio or video processing (see “XMOS Unveils First Software-Defined Silicon”).

1. XMOS's xCORE architecture supports multiple logical cores connected by an on-chip switch.

The 32-bit cores are grouped into tiles of eight cores. Each core can issue up to two instructions per clock cycle into the execution pipeline (see “Dual-Issue Multicore SOC Handles Soft Peripherals”). Every core cycle is able to execute an instruction that pauses for an external event.

I was able to check out the programming environment for the xCORE using the xCORE-200 eXplorerKIT (Fig. 2). This has a midrange, 16-core chip with Gigabit Ethernet support. You can solder headers to get access to all of the chip’s pins. The kit includes a header socket that enables use of the XTAG3 JTAG interface for low-level debugging.

Getting started with eXplorerKIT requires downloading the latest xTIMEcomposer Studio. This Eclipse-based IDE incorporates the xC compiler as well as LLVM C and C++ compilers. The xDEBUG is a GDB debugger with support for xCORE. A cycle-accurate debugger called xSIM can be used to try out the architecture without needing the kit.

2. The XMOS xCORE-200 eXplorerKIT features a 16-core chip with Gigabit Ethernet support.

The xSCOPE support is a real-time logic analyzer that’s very handy for applications dealing with hard real-time interface chores. This complements the XTA static-analysis tool designed to address timing issues. The tool is also ideal for working through real-time interfaces.

No surprises lurk when getting the development software to talk to the platform (it works with the XTAG3). Likewise, xDEBUG will be familiar to anyone using gdb. It exposes a little more xCORE specific hardware, but this is typical for any gdb debugger enhancements for a particular micro.

The main difference is the xC compiler and the soft-peripheral support that’s covered by a collection of downloadable app notes. The soft peripherals take advantage of one or more cores. It’s relatively easy to adjust the code to use different pins or provide new functionality.

The xC compiler exposes the parallel programming and interprocess communication support. Low-level parallel constructs are provided; for example, par { f(); g(); h(); } will run three functions in parallel. The statement completes after completion of all three functions. 

There are two constructs for interprocess communication. The low-level interface is called a channel and it maps to the hardware support. This example shows the send/receive semantics that use the <: and :> operators:

chan c;

int result;

par {

  c <: 10;

  c :> result;

}

 

Channel exchange is synchronized and a destination will wait until data is provided. Likewise, a source will wait if the destination isn’t waiting for data.

The more-flexible interfaces, which are built on channels, also use a more-conventional object.method syntax instead of special operators. An interface can wait for different data sources and patterns using a select statement. Most programmers will utilize an interface instead of channels. Channels are typically found in low-level programming support for device drivers, etc.

New xCORE developers will definitely want to take time to run through at least a few of the app notes. The xCORE can be used as a compute platform with lots of cores as a conventional microprocessor platform. However, the system’s real advantage emerges when utilizing the parallel features. This often means breaking out the trace support and other debug analysis tools, but that tends to be all for the good.

I haven’t had a chance to do more than run through a few sample apps. Nonetheless, it’s definitely a fun platform to work with. It’s also much more powerful than the 8-bit platform I had used that depended on soft peripherals. If you really want to see some neat xCORE applications, check out the EtherCAT and AVB support.

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