Cypress’ new 16-Mbit Fast Asynchronous SRAM with on-chip error-correcting code (ECC) is designed to achieve the highest levels of data reliability, without the need for additional error correction chips. The device touts best-in-class soft error rate performance, ensuring data reliability in a variety of industrial, military, communication, data processing, medical, consumer and automotive applications. Also available is a new Fast SRAM with PowerSnooze family that combines the 10-ns access times of Fast SRAMs with low standby power comparable to that of the MoBL family. PowerSnooze is an additional power-saving Deep Sleep mode that achieves 12 uA (typical) deep-sleep current for a 16 Mb SRAM. The 16 Mb Fast SRAM with PowerSnooze also offers the on-chip ECC. Offered in x8, x16 and x32 configurations, the Asynchronous SRAMs operate at 1.8 V, 3 V and 5 V over -40°C to +85°C (Industrial) and -40°C to +125°C (Automotive-E) temperature ranges. Available in RoHS compliant 48-pin TSOP I, 48-ball VFBGA, 119-ball BGA and 54-pin TSOP II packages, the 16 Mb Fast Asynchronous SRAM and the 16 Mb Fast Asynchronous SRAM with PowerSnooze are currently sampling, with production expected in July.
16 Mb Asynchronous SRAM Includes On-Chip Error-Correcting Code
16 Mb Fast Asynchronous SRAM with on-chip ECC is designed to achieve the highest levels of data reliability without the need for additional error correction chips.